From WikiChip
Difference between revisions of "intel/microarchitectures/rocket lake"
(→Brands: 50px|link=intel/core_i9 fix intel/microarchitectures/alder_lake 4-8) |
|||
(22 intermediate revisions by 13 users not shown) | |||
Line 5: | Line 5: | ||
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
+ | |introduction=March 16, 2021 | ||
|process=14 nm | |process=14 nm | ||
|cores=4 | |cores=4 | ||
+ | |cores 2=6 | ||
+ | |cores 3=8 | ||
|type=Superscalar | |type=Superscalar | ||
|type 2=Superpipeline | |type 2=Superpipeline | ||
Line 46: | Line 49: | ||
|extension 29=SGX | |extension 29=SGX | ||
|extension 30=MPX | |extension 30=MPX | ||
− | |l1i= | + | |extension 31=AVX512F |
+ | |extension 32=SHA | ||
+ | |l1i=48 KiB | ||
|l1i per=core | |l1i per=core | ||
− | |l1i desc= | + | |l1i desc=12-way set associative |
|l1d=32 KiB | |l1d=32 KiB | ||
|l1d per=core | |l1d per=core | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
− | |l2= | + | |l2=512 KiB |
|l2 per=core | |l2 per=core | ||
− | |l2 desc= | + | |l2 desc=8-way set associative |
|l3=2 MiB | |l3=2 MiB | ||
|l3 per=core | |l3 per=core | ||
− | |l3 desc= | + | |l3 desc=16-way set associative |
− | | | + | |core name=Cypress Cove |
− | |||
− | |||
|predecessor=Comet Lake | |predecessor=Comet Lake | ||
|predecessor link=intel/microarchitectures/comet lake | |predecessor link=intel/microarchitectures/comet lake | ||
+ | |successor=Alder Lake | ||
+ | |successor link=intel/microarchitectures/alder_lake | ||
+ | |contemporary=Tiger Lake | ||
+ | |contemporary link=intel/microarchitectures/tiger_lake | ||
}} | }} | ||
− | '''Rocket Lake''' ('''RKL''') is a | + | '''Rocket Lake''' ('''RKL''') is a [[microarchitecture]] designed by [[Intel]] as a successor to {{\\|Comet Lake}} for desktops and single-socket servers. |
Line 78: | Line 85: | ||
== Brands == | == Brands == | ||
− | Intel | + | Intel has released Rocket Lake under the following brand families: |
{| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | {| class="wikitable tc4 tc5 tc6 tc7 tc8" style="text-align: center;" | ||
Line 84: | Line 91: | ||
! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features | ! rowspan="2" | Logo !! rowspan="2" | Family !! rowspan="2" | General Description !! colspan="6" | Differentiating Features | ||
|- | |- | ||
− | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{intel| | + | ! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{x86|AVX512}} !! {{intel|Thermal Velocity Boost|TVB}} !! [[ECC]] |
|- | |- | ||
− | | [[File:core | + | | [[File:core i5 logo (2020).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:core | + | | [[File:core i7 logo (2020).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}} |
|- | |- | ||
− | | [[File:core | + | | [[File:core i9 logo (2020).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} |
+ | |- | ||
+ | | [[File:xeon logo (2021).png|50px|link=intel/xeon]] || {{intel|Xeon}} || 1S Server & Workstation || [[quad-core|4]]-[[octa-core|8]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}} | ||
|} | |} | ||
== Release Dates == | == Release Dates == | ||
− | + | Rocket Lake was officially introduced on March 16, 2021 and went on sale from March 30, 2021. | |
+ | Limited quantities of the Core i7-11700K were (accidentally?) available through the German reseller Mindfactory on March 6, 2021. | ||
+ | |||
+ | The Xeon W-1300 Line using Rocket Lake is expected to be officially launched in Q3/2021. | ||
== Compatibility== | == Compatibility== | ||
{{empty section}} | {{empty section}} | ||
+ | Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with [[Comet Lake]]. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake. | ||
== Compiler support == | == Compiler support == | ||
Line 104: | Line 117: | ||
! Compiler !! Arch-Specific || Arch-Favorable | ! Compiler !! Arch-Specific || Arch-Favorable | ||
|- | |- | ||
− | | [[ICC]] || <code>-march= | + | | [[ICC]] || <code>-march=?</code> || <code>-mtune=?</code> |
|- | |- | ||
− | | [[GCC]] || <code>-march= | + | | [[GCC]] || <code>-march=rocketlake</code> || <code>-mtune=rocketlake</code> |
|- | |- | ||
− | | [[LLVM]] || <code>-march= | + | | [[LLVM]] || <code>-march=?</code> || <code>-mtune=?</code> |
|- | |- | ||
− | | [[Visual Studio]] || <code>/arch: | + | | [[Visual Studio]] || <code>/arch:AVX512</code> || <code>/?</code> |
|} | |} | ||
=== CPUID === | === CPUID === | ||
− | {{ | + | {{further|intel/cpuid|l1=Intel CPUIDs}} |
+ | {| class="wikitable tc1 tc2 tc3 tc4 tc5" | ||
+ | ! Core !! Extended<br>Family !! Family !! Extended<br>Model !! Model !! Stepping | ||
+ | |- | ||
+ | | rowspan="2" | {{intel|Rocket Lake S|S|l=core}} || 0 || 0x6 || 0xA || 0x7 || 0x0-0x1 | ||
+ | |- | ||
+ | | colspan="5" | Family 6 Model 167 Stepping 0-1<br>Stepping: A0=0, B0=1 | ||
+ | |} | ||
== Architecture == | == Architecture == | ||
− | === Key changes from {{\\| | + | === Key changes from {{\\|Comet Lake}}=== |
− | {{ | + | {{future information}} |
+ | * Core | ||
+ | ** {{\\|Skylake}} '''➡''' {{\\|Cypress Cove}} | ||
+ | |||
+ | * GPU | ||
+ | ** {{intel|Gen 9.5|l=arch}} '''➡''' {{intel|Gen12|l=arch}} (Xe) | ||
+ | ** 32 EUs up from 24 EUs | ||
+ | |||
+ | * Display | ||
+ | ** [[DisplayPort]] 1.4a (from DisplayPort 1.2) | ||
+ | ** [[HDMI]] 2.0b (from HDMI 1.4b) | ||
+ | |||
+ | * I/O | ||
+ | ** PCIe 4.0 (from 3.0) | ||
+ | |||
+ | * Memory | ||
+ | ** Faster memory for mainstream desktops (i.e., {{intel|Rocket Lake S|l=core}}) DDR4-3200 (from DDR4-2933) | ||
+ | |||
+ | * Chipset | ||
+ | ** {{intel|Cannon Point|400 Series chipset|l=chipset}} → {{intel|Rocket Point|500 Series chipset|l=chipset}} | ||
+ | *** 2.5G Ethernet (Foxville) support | ||
+ | *** Integrated WiFi 6 AX201 (GiG+) support via {{intel|CNVi}} | ||
+ | |||
+ | * Packaging | ||
+ | ** [[Die thinning]] on top-end SKUs for better heat removal | ||
== See also == | == See also == | ||
− |
Latest revision as of 12:55, 20 November 2021
Edit Values | |
Rocket Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | March 16, 2021 |
Process | 14 nm |
Core Configs | 4, 6, 8 |
Pipeline | |
Type | Superscalar, Superpipeline |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Decode | 5-way |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX512F, SHA |
Cache | |
L1I Cache | 48 KiB/core 12-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 512 KiB/core 8-way set associative |
L3 Cache | 2 MiB/core 16-way set associative |
Cores | |
Core Names | Cypress Cove |
Succession | |
Contemporary | |
Tiger Lake |
Rocket Lake (RKL) is a microarchitecture designed by Intel as a successor to Comet Lake for desktops and single-socket servers.
Contents
Codenames[edit]
Core | Description | Graphics | Target |
---|---|---|---|
Rocket Lake S | Mainstream performance | GT2 | Desktop performance to value, AiOs, and minis |
Rocket Lake U | Ultra-low power | GT2 | Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room |
Brands[edit]
Intel has released Rocket Lake under the following brand families:
Logo | Family | General Description | Differentiating Features | ||||||
---|---|---|---|---|---|---|---|---|---|
Cores | HT | AVX | AVX2 | AVX512 | TVB | ECC | |||
![]() |
Core i5 | Mid-range Performance | Hexa | ✔ | ✔ | ✔ | ✔ | ✘ | ✘ |
![]() |
Core i7 | High-end Performance | Octa | ✔ | ✔ | ✔ | ✔ | ✘ | ✘ |
![]() |
Core i9 | High-end Performance | Octa | ✔ | ✔ | ✔ | ✔ | ✔ | ✘ |
50px | Xeon | 1S Server & Workstation | 4-8 | ✔ | ✔ | ✔ | ✔ | ✘ | ✔ |
Release Dates[edit]
Rocket Lake was officially introduced on March 16, 2021 and went on sale from March 30, 2021. Limited quantities of the Core i7-11700K were (accidentally?) available through the German reseller Mindfactory on March 6, 2021.
The Xeon W-1300 Line using Rocket Lake is expected to be officially launched in Q3/2021.
Compatibility[edit]
![]() |
This section is empty; you can help add the missing info by editing this page. |
Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with Comet Lake. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake.
Compiler support[edit]
Compiler | Arch-Specific | Arch-Favorable |
---|---|---|
ICC | -march=? |
-mtune=?
|
GCC | -march=rocketlake |
-mtune=rocketlake
|
LLVM | -march=? |
-mtune=?
|
Visual Studio | /arch:AVX512 |
/?
|
CPUID[edit]
- Further information: Intel CPUIDs
Core | Extended Family |
Family | Extended Model |
Model | Stepping |
---|---|---|---|---|---|
S | 0 | 0x6 | 0xA | 0x7 | 0x0-0x1 |
Family 6 Model 167 Stepping 0-1 Stepping: A0=0, B0=1 |
Architecture[edit]
Key changes from Comet Lake[edit]
- Core
- Display
- DisplayPort 1.4a (from DisplayPort 1.2)
- HDMI 2.0b (from HDMI 1.4b)
- I/O
- PCIe 4.0 (from 3.0)
- Memory
- Faster memory for mainstream desktops (i.e., Rocket Lake S) DDR4-3200 (from DDR4-2933)
- Chipset
- 400 Series chipset → 500 Series chipset
- 2.5G Ethernet (Foxville) support
- Integrated WiFi 6 AX201 (GiG+) support via CNVi
- 400 Series chipset → 500 Series chipset
- Packaging
- Die thinning on top-end SKUs for better heat removal
See also[edit]
Facts about "Rocket Lake - Microarchitectures - Intel"
codename | Rocket Lake + |
core count | 4 +, 6 + and 8 + |
designer | Intel + |
first launched | March 16, 2021 + |
full page name | intel/microarchitectures/rocket lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Rocket Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |