From WikiChip
Difference between revisions of "samsung/exynos/9820"
< samsung‎ | exynos

(Created page with "Exynos 9820 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung in late 2018 and introduced in early 2019 as a successor to the Exynos 9810....")
 
(Undo revision 98778, did not work)
 
(30 intermediate revisions by 11 users not shown)
Line 1: Line 1:
−
Exynos 9820 is a 64-bit octa-core ARM high performance mobile system on a chip
+
{{samsung title|Exynos 9820}}
−
designed by Samsung in late 2018 and introduced in early 2019 as a successor to the Exynos 9810.
+
{{chip
−
The processor is fabricated on Samsung's 8 nm LPP (Low Power Plus) FinFET process
+
|name=Exynos 9820
−
and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose M4,
+
|image=exynos 9820 (front).png
−
2 ARM Cortex-A75 and 4 Cortex-A55 little cores.
+
|back image size=exynos 9820 (back).png
−
The chip supports up to 11.6 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G76 MP12 GPU.
+
|designer=Samsung
−
The 9820 incorporates an LTE modem supporting cat 20 8CA 2Gbps download and cat 20 3CA 316 Mbps upload.
+
|designer 2=ARM Holdings
 +
|manufacturer=Samsung
 +
|model number=9820
 +
|market=Mobile
 +
|first announced=November 14, 2018
 +
|first launched=January, 2019
 +
|family=Exynos
 +
|series=Exynos 9
 +
|frequency=2 @ 2,730 MHz
 +
|frequency 2=2 @ 2,310 MHz
 +
|frequency 3=4 @ 1,950 MHz
 +
|isa=ARMv8.2
 +
|isa family=ARM
 +
|microarch=Exynos M4
 +
|microarch 2=Cortex-A75
 +
|microarch 3=Cortex-A55
 +
|core name=Cheetah
 +
|core name 2=Cortex-A75
 +
|core name 3=Cortex-A55
 +
|process=8 nm
 +
|technology=CMOS
 +
|die area=127 mm²
 +
|word size=64 bit
 +
|core count=8
 +
|thread count=8
 +
|max memory=12 GiB
 +
|max cpus=1
 +
|predecessor=Exynos 9810
 +
|predecessor link=samsung/exynos/9810
 +
|successor=Exynos 990
 +
|successor link=samsung/exynos/990
 +
|contemporary=Exynos 9825
 +
|contemporary link=samsung/exynos/9825
 +
}}
 +
'''Exynos 9820''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in early [[2019]]. The processor is fabricated on Samsung's [[8 nm process|8nm]] [[8LPP|LPP (Low Power Plus)]] FinFET process and features [[8 cores]] in a tri-cluster configuration consisting of 2 {{samsung|Mongoose 4|l=arch}} [[big cores]] and 2 {{armh|Cortex-A75|l=arch}} [[middle cores]] and 4 Cortex-A55 [[little cores]]. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a {{armh|Mali-G76}} MP12 GPU. The 9820 incorporates an LTE modem supporting cat 20 download and upload.
 +
 
 +
 
 +
== Cache ==
 +
{{main|samsung/microarchitectures/m4#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a76#Memory_Hierarchy|l1=Mongoose  § Cache||l2=Cortex-A76 § Cache}}
 +
For the {{samsung|Mongoose 4|l=arch}} core cluster:
 +
{{cache size
 +
|l1 cache=192 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=2x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=2x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=1 MiB
 +
|l2 break=2x512 KiB
 +
|l2 desc=16-way set associative
 +
|l3 cache=2 MiB
 +
|l3 break=2x1 MiB
 +
}}
 +
 
 +
For the {{armh|Cortex-A75|l=arch}} cluster:
 +
 
 +
{{cache size
 +
|l1 cache=256 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=2x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=128 KiB
 +
|l1d break=2x64 KiB
 +
|l1d desc=16-way set associative
 +
|l2 cache=512 KiB
 +
|l2 break=2x256 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 
 +
 
 +
For the {{armh|Cortex-A55|l=arch}} cluster:
 +
 
 +
{{cache size
 +
|l1 cache=
 +
|l1i cache=
 +
|l1i break=
 +
|l1i desc=
 +
|l1d cache=
 +
|l1d break=
 +
|l1d desc=
 +
|l2 cache=
 +
|l2 break=
 +
|l2 desc=
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR4X-3600
 +
|ecc=No
 +
|max mem=12 GiB
 +
|controllers=4
 +
|channels=4
 +
|width=16 bit
 +
|max bandwidth=26.82 GiB/s
 +
|frequency=1800 MHz
 +
|bandwidth schan=6.71 GiB/s
 +
|bandwidth dchan=13.41 GiB/s
 +
|bandwidth qchan=26.82 GiB/s
 +
}}
 +
 
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Mali-G76
 +
| device id          =
 +
| designer            = ARM Holdings
 +
| execution units    = 12
 +
| max displays        = 2
 +
| max memory          =
 +
| min frequency      = 156MHz
 +
| max frequency      = 702MHz
 +
 
 +
| output crt          =
 +
| output sdvo        =
 +
| output dsi          = Yes
 +
| output edp          =
 +
| output dp          = Yes
 +
| output hdmi        =
 +
| output vga          =
 +
| output dvi          =
 +
 
 +
| directx ver        = 12
 +
| opengl ver        =
 +
| opengl es ver      = 3.2
 +
| openvg ver        = 1.1
 +
| opencl ver        = 2.1
 +
| vulkan ver        = 1.1.108
 +
| hdmi ver          =
 +
| dp ver            =
 +
| edp ver            =
 +
| max res hdmi      =
 +
| max res hdmi freq  =
 +
| max res dp        =
 +
| max res dp freq    =
 +
| max res edp        =
 +
| max res edp freq  =
 +
| max res vga        =
 +
| max res vga freq  =
 +
}}
 +
 
 +
 
 +
{| class=wikitable
 +
|-
 +
! Codec !! Encode !! Decode
 +
|-
 +
| [[HEVC]] (H.265) || {{tchk|yes}} || {{tchk|yes}}
 +
|-
 +
| [[MPEG-4 AVC]] (H.264) || {{tchk|yes}} || {{tchk|yes}}
 +
|-
 +
| [[VP9]] || {{tchk|yes}} || {{tchk|yes}}
 +
|-
 +
|}
 +
 
 +
All at 4K UHD 150fps.
 +
 
 +
== NPU ==
 +
The Exynos 9820 features Samsung's homegrown NPU instead of the licensed [[DeePhi]] DLA. The new NPU features 1,024 MACs split between two execution cores. The new NPU is capable of a peaking compute of two teraOPS.
 +
 
 +
== Wireless ==
 +
{{wireless links
 +
| 2g                =
 +
| csd              =
 +
| gsm              =
 +
| gprs              =
 +
| edge              =
 +
| cdmaone          =
 +
| is-95a            =
 +
| is-95b            =
 +
| 3g                =
 +
| cdma2000          =
 +
| cdma2000 1x      =
 +
| cdma2000 1xev-do  =
 +
| cdma2000 1x adv  =
 +
| umts              =
 +
| wcdma            = 
 +
| td-scdma          =
 +
| dc-hsdpa          =
 +
| hsdpa            =
 +
| hsupa            =
 +
| 4g                = Yes
 +
| lte a            = Yes
 +
| e-utran          =
 +
| ue cat dl        = 20
 +
| ue cat dl rate    = 2000 Mbps
 +
| ue cat ul        = 20
 +
| ue cat ul rate    = 316 Mbps
 +
}}
 +
 
 +
== ISP ==
 +
* 22MP Rear
 +
* 22MP Front
 +
* 16MP+16MP Dual
 +
 
 +
== Features ==
 +
{{arm features
 +
|thumb=No
 +
|thumb2=No
 +
|thumbee=No
 +
|vfpv1=No
 +
|vfpv2=No
 +
|vfpv3=No
 +
|vfpv3-d16=No
 +
|vfpv3-f16=No
 +
|vfpv4=No
 +
|vfpv4-d16=No
 +
|vfpv5=No
 +
|neon=Yes
 +
|trustzone=No
 +
|jazelle=No
 +
|wmmx=No
 +
|wmmx2=No
 +
|pmuv3=No
 +
|crc32=Yes
 +
|crypto=Yes
 +
|fp=Yes
 +
|fp16=No
 +
|profile=No
 +
|ras=No
 +
|simd=No
 +
|rdm=No
 +
}}
 +
 
 +
== Utilizing devices ==
 +
* [[used by::Samsung Galaxy S10]]
 +
* [[used by::Samsung Galaxy S10 5G]]
 +
* [[used by::Samsung Galaxy S10+]]
 +
* [[used by::Samsung Galaxy S10e]]
 +
 
 +
== Documents ==
 +
* [[:File:MobileProcessor-9-Series-9820.pdf|Product Brief]]

Latest revision as of 08:43, 28 April 2021

Edit Values
Exynos 9820
exynos 9820 (front).png
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number9820
MarketMobile
IntroductionNovember 14, 2018 (announced)
January, 2019 (launched)
General Specs
FamilyExynos
SeriesExynos 9
Frequency2 @ 2,730 MHz, 2 @ 2,310 MHz, 4 @ 1,950 MHz
Microarchitecture
ISAARMv8.2 (ARM)
MicroarchitectureExynos M4, Cortex-A75, Cortex-A55
Core NameCheetah, Cortex-A75, Cortex-A55
Process8 nm
TechnologyCMOS
Die127 mm²
Word Size64 bit
Cores8
Threads8
Max Memory12 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Succession
Contemporary
Exynos 9825

Exynos 9820 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in early 2019. The processor is fabricated on Samsung's 8nm LPP (Low Power Plus) FinFET process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose 4 big cores and 2 Cortex-A75 middle cores and 4 Cortex-A55 little cores. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G76 MP12 GPU. The 9820 incorporates an LTE modem supporting cat 20 download and upload.


Cache[edit]

Main articles: Mongoose § Cache and Cortex-A76 § Cache

For the Mongoose 4 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x512 KiB16-way set associative 
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB  

For the Cortex-A75 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
2x64 KiB16-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associative 


For the Cortex-A55 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3600
Supports ECCNo
Max Mem12 GiB
Frequency1800 MHz
Controllers4
Channels4
Width16 bit
Max Bandwidth26.82 GiB/s
27,463.68 MiB/s
28.798 GB/s
28,797.756 MB/s
0.0262 TiB/s
0.0288 TB/s
Bandwidth
Single 6.71 GiB/s
Double 13.41 GiB/s
Quad 26.82 GiB/s

Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G76
DesignerARM Holdings
Execution Units12Max Displays2
Burst Frequency702MHz
0.702 GHz
702,000 KHz
OutputDP, DSI
Standards
DirectX12
OpenCL2.1
OpenGL ES3.2
OpenVG1.1
Vulkan1.1.108


Codec Encode Decode
HEVC (H.265) ✔ ✔
MPEG-4 AVC (H.264) ✔ ✔
VP9 ✔ ✔

All at 4K UHD 150fps.

NPU[edit]

The Exynos 9820 features Samsung's homegrown NPU instead of the licensed DeePhi DLA. The new NPU features 1,024 MACs split between two execution cores. The new NPU is capable of a peaking compute of two teraOPS.

Wireless[edit]

Antu network-wireless-connected-100.svgWireless Communications
Cellular
4G
LTE Advanced
UE Cat DL20 (2000 Mbps)
UE Cat UL20 (316 Mbps)

ISP[edit]

  • 22MP Rear
  • 22MP Front
  • 16MP+16MP Dual

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension

Utilizing devices[edit]

  • Samsung Galaxy S10
  • Samsung Galaxy S10 5G
  • Samsung Galaxy S10+
  • Samsung Galaxy S10e

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/9820&oldid=98779"
Facts about "Exynos 9820 - Samsung"
RDF feed
core count8 +
core nameCheetah +, Cortex-A75 + and Cortex-A55 +
designerSamsung + and ARM Holdings +
die area127 mm² (0.197 in², 1.27 cm², 127,000,000 µm²) +
familyExynos +
first announcedNovember 14, 2018 +
first launchedJanuary 2019 +
full page namesamsung/exynos/9820 +
has 4g supporttrue +
has ecc memory supportfalse +
has lte advanced supporttrue +
instance ofmicroprocessor +
integrated gpuMali-G76 +
integrated gpu designerARM Holdings +
integrated gpu execution units12 +
integrated gpu max frequency702 MHz (0.702 GHz, 702,000 KHz) +
isaARMv8.2 +
isa familyARM +
l1$ size192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative + and 16-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative + and 8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateJanuary 2019 +
main imageFile:exynos 9820 (front).png +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max memory12,288 MiB (12,582,912 KiB, 12,884,901,888 B, 12 GiB, 0.0117 TiB) +
max memory bandwidth26.82 GiB/s (27,463.68 MiB/s, 28.798 GB/s, 28,797.756 MB/s, 0.0262 TiB/s, 0.0288 TB/s) +
max memory channels4 +
microarchitectureExynos M4 +, Cortex-A75 + and Cortex-A55 +
model number9820 +
nameExynos 9820 +
process8 nm (0.008 μm, 8.0e-6 mm) +
seriesExynos 9 +
smp max ways1 +
supported memory typeLPDDR4X-3600 +
technologyCMOS +
thread count8 +
used bySamsung Galaxy S10 +, Samsung Galaxy S10 5G +, Samsung Galaxy S10+ + and Samsung Galaxy S10e +
user equipment category downlink20 +
user equipment category uplink20 +
word size64 bit (8 octets, 16 nibbles) +