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Difference between revisions of "intel/xeon bronze/3104"
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{{intel title|Xeon Bronze 3104}}
 
{{intel title|Xeon Bronze 3104}}
−
{{mpu
+
{{chip
−
|future=Yes
 
 
|name=Xeon Bronze 3104
 
|name=Xeon Bronze 3104
−
|no image=Yes
+
|image=skylake sp (basic).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=3104
 
|model number=3104
−
|part number=CD8067303562000
+
|part number=BX806733104
 +
|part number 2=CD8067303562000
 +
|s-spec=SR3GM
 +
|s-spec qs=QN0D
 
|market=Server
 
|market=Server
 +
|market 2=Workstation
 +
|first announced=July 11, 2017
 +
|first launched=July 11, 2017
 +
|release price=$213.00
 
|family=Xeon Bronze
 
|family=Xeon Bronze
 
|series=3000
 
|series=3000
 
|locked=Yes
 
|locked=Yes
 
|frequency=1,700 MHz
 
|frequency=1,700 MHz
 +
|clock multiplier=17
 +
|cpuid=0x50654
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
−
|microarch=Skylake
+
|microarch=Skylake (server)
 
|platform=Purley
 
|platform=Purley
 
|chipset=Lewisburg
 
|chipset=Lewisburg
 
|core name=Skylake SP
 
|core name=Skylake SP
 
|core family=6
 
|core family=6
 +
|core stepping=U0
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
 
|word size=64 bit
 
|word size=64 bit
 
|core count=6
 
|core count=6
−
|thread count=12
+
|thread count=6
−
|package module 1={{packages/intel/fclga-3647}}
+
|max memory=768 GiB
 +
|max cpus=2
 +
|smp interconnect=UPI
 +
|smp interconnect links=2
 +
|smp interconnect rate=9.6 GT/s
 +
|tdp=85 W
 +
|tcase min=0 °C
 +
|tcase max=78 °C
 +
|dts min=0 °C
 +
|dts max=89 °C
 +
|package name 1=intel,fclga_3647
 +
|successor=Xeon Bronze 3204
 +
|successor link=intel/xeon_bronze/3204
 
}}
 
}}
−
'''Xeon Bronze 3104''' is a {{arch|64}} [[hexa-core]] [[x86]] server microprocessor set to be introduced by [[Intel]] in July 2017.
+
'''Xeon Bronze 3104''' is a {{arch|64}} [[hexa-core]] [[x86]] dual-socket entry-level server and workstation microprocessor introduced by [[Intel]] in mid-2017. The Bronze 3104, which is based on the server configuration of the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]] sports 1 {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory.
−
{{unknown features}}
 
  
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/skylake#Memory_Hierarchy|l1=Skylake § Cache}}
+
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
 
{{cache size
 
{{cache size
 
|l1 cache=384 KiB
 
|l1 cache=384 KiB
Line 50: Line 70:
 
|l3 policy=write-back
 
|l3 policy=write-back
 
}}
 
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2133
 +
|ecc=Yes
 +
|max mem=768 GiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=95.37 GiB/s
 +
|bandwidth schan=15.89 GiB/s
 +
|bandwidth dchan=31.79 GiB/s
 +
|bandwidth qchan=63.58 GiB/s
 +
|bandwidth hchan=95.37 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 48
 +
| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=No
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=1,700 MHz
 +
|freq_1=1,700 MHz
 +
|freq_2=1,700 MHz
 +
|freq_3=1,700 MHz
 +
|freq_4=1,700 MHz
 +
|freq_5=1,700 MHz
 +
|freq_6=1,700 MHz
 +
|freq_avx2_base=1,300 MHz
 +
|freq_avx2_1=1,300 MHz
 +
|freq_avx2_2=1,300 MHz
 +
|freq_avx2_3=1,300 MHz
 +
|freq_avx2_4=1,300 MHz
 +
|freq_avx2_5=1,300 MHz
 +
|freq_avx2_6=1,300 MHz
 +
|freq_avx512_base=800 MHz
 +
|freq_avx512_1=800 MHz
 +
|freq_avx512_2=800 MHz
 +
|freq_avx512_3=800 MHz
 +
|freq_avx512_4=800 MHz
 +
|freq_avx512_5=800 MHz
 +
|freq_avx512_6=800 MHz
 +
}}
 +
 +
[[Category:microprocessor models by intel based on skylake low core count die]]

Latest revision as of 22:21, 28 December 2019

Edit Values
Xeon Bronze 3104
skylake sp (basic).png
General Info
DesignerIntel
ManufacturerIntel
Model Number3104
Part NumberBX806733104,
CD8067303562000
S-SpecSR3GM
QN0D (QS)
MarketServer, Workstation
IntroductionJuly 11, 2017 (announced)
July 11, 2017 (launched)
Release Price$213.00
ShopAmazon
General Specs
FamilyXeon Bronze
Series3000
LockedYes
Frequency1,700 MHz
Clock multiplier17
CPUID0x50654
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
PlatformPurley
ChipsetLewisburg
Core NameSkylake SP
Core Family6
Core SteppingU0
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores6
Threads6
Max Memory768 GiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
InterconnectUPI
Interconnect Links2
Interconnect Rate9.6 GT/s
Electrical
TDP85 W
Tcase0 °C – 78 °C
TDTS0 °C – 89 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Bronze 3104 is a 64-bit hexa-core x86 dual-socket entry-level server and workstation microprocessor introduced by Intel in mid-2017. The Bronze 3104, which is based on the server configuration of the Skylake microarchitecture and is manufactured on a 14 nm process sports 1 AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor, which operates at 1.7 GHz with a TDP of 85 W, supports up 768 GiB of hexa-channel DDR4-2133 ECC memory.

Cache[edit]

Main article: Skylake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
6x32 KiB8-way set associativewrite-back
L2$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  6x1 MiB16-way set associativewrite-back
L3$8.25 MiB
8,448 KiB
8,650,752 B
0.00806 GiB
  6x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem768 GiB
Controllers2
Channels6
Max Bandwidth95.37 GiB/s
97,658.88 MiB/s
102.403 GB/s
102,402.758 MB/s
0.0931 TiB/s
0.102 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s
Quad 63.58 GiB/s
Hexa 95.37 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456
Normal1,700 MHz1,700 MHz1,700 MHz1,700 MHz1,700 MHz1,700 MHz1,700 MHz
AVX21,300 MHz1,300 MHz1,300 MHz1,300 MHz1,300 MHz1,300 MHz1,300 MHz
AVX512800 MHz800 MHz800 MHz800 MHz800 MHz800 MHz800 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_bronze/3104&oldid=95107"
Facts about "Xeon Bronze 3104 - Intel"
RDF feed
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size192 KiB (196,608 B, 0.188 MiB) +
l1i$ description8-way set associative +
l1i$ size192 KiB (196,608 B, 0.188 MiB) +
l2$ description16-way set associative +
l2$ size6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ description11-way set associative +
l3$ size8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) +