Semiconductor & Computer Engineering
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Difference between revisions of "amd/epyc/7282"
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|series=7002 | |series=7002 | ||
|locked=Yes | |locked=Yes | ||
| − | |frequency=2 | + | |frequency=2.000 MHz |
| − | |turbo frequency=3 | + | |turbo frequency=3.200 MHz |
|clock multiplier=20 | |clock multiplier=20 | ||
|isa=x86-64 | |isa=x86-64 | ||
Revision as of 12:28, 7 August 2019
| Edit Values | |
| EPYC 7282 | |
| General Info | |
| Designer | AMD |
| Manufacturer | TSMC, GlobalFoundries |
| Model Number | 7282 |
| Part Number | 100-000000078 |
| Market | Server |
| Introduction | August 7, 2019 (announced) August 7, 2019 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | EPYC |
| Series | 7002 |
| Locked | Yes |
| Frequency | 2.000 MHz |
| Turbo Frequency | 3.200 MHz |
| Clock multiplier | 20 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Zen 2 |
| Core Name | Rome |
| Core Family | 23 |
| Process | 7 nm, 14 nm |
| Technology | CMOS |
| MCP | Yes (3 dies) |
| Word Size | 64 bit |
| Cores | 16 |
| Threads | 32 |
| Max Memory | 4 TiB |
| Multiprocessing | |
| Max SMP | 2-Way (Multiprocessor) |
| Electrical | |
| TDP | 120 W |
| Packaging | |
| Package | SP3, FCLGA-4094 (FC-OLGA) |
| Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
| Pitch | 0.87 mm × 1 mm |
| Contacts | 4094 |
| Socket | SP3, LGA-4094 |
| Succession | |
EPYC 7282 is a 64-bit hexadeca-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7282 has a TDP of 120 W with a base frequency of 2 GHz and a boost frequency of up to 3.2 GHz. This processor supports up to two-way SMP and up to 4 TiB of eight channels DDR4-3200 memory per socket.
Contents
Cache
- Main article: Zen 2 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Features
[Edit/Modify Supported Features]
Facts about "EPYC 7282 - AMD"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 7282 - AMD#pcie + |
| base frequency | 2 MHz (0.002 GHz, 2,000 kHz) + |
| clock multiplier | 20 + |
| core count | 16 + |
| core family | 23 + |
| core name | Rome + |
| designer | AMD + |
| die count | 3 + |
| family | EPYC + |
| first announced | August 7, 2019 + |
| first launched | August 7, 2019 + |
| full page name | amd/epyc/7282 + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has amd amd-v technology | true + |
| has amd amd-vi technology | true + |
| has amd precision boost 2 | true + |
| has amd secure encrypted virtualization technology | true + |
| has amd secure memory encryption technology | true + |
| has amd sensemi technology | true + |
| has amd transparent secure memory encryption technology | true + |
| has ecc memory support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 + |
| has locked clock multiplier | true + |
| has simultaneous multithreading | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| is multi-chip package | true + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) + |
| l3$ size | 64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) + |
| ldate | August 7, 2019 + |
| manufacturer | TSMC + and GlobalFoundries + |
| market segment | Server + |
| max cpu count | 2 + |
| max memory | 4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) + |
| max memory bandwidth | 190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) + |
| max memory channels | 8 + |
| microarchitecture | Zen 2 + |
| model number | 7282 + |
| name | EPYC 7282 + |
| package | SP3 + and FCLGA-4094 + |
| part number | 100-000000078 + |
| process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
| series | 7002 + |
| smp max ways | 2 + |
| socket | SP3 + and LGA-4094 + |
| supported memory type | DDR4-3200 + |
| tdp | 120 W (120,000 mW, 0.161 hp, 0.12 kW) + |
| technology | CMOS + |
| thread count | 32 + |
| turbo frequency | 3.2 MHz (0.0032 GHz, 3,200 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |