From WikiChip
Difference between revisions of "amd/epyc/7252"
< amd‎ | epyc

Line 38: Line 38:
 
}}
 
}}
 
'''EPYC 7252''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
 
'''EPYC 7252''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
 +
 +
== Cache ==
 +
{{main|amd/microarchitectures/zen 2#Memory_Hierarchy|l1=Zen 2 § Cache}}
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l2 cache=4 MiB
 +
|l2 break=8x512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=64 MiB
 +
|l3 break=4x16 MiB
 +
}}

Revision as of 15:24, 6 August 2019

Edit Values
EPYC 7252
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
Model Number7252
Part Number100-000000080
MarketServer
IntroductionAugust 7, 2019 (announced)
August 7, 2019 (launched)
ShopAmazon
General Specs
FamilyEPYC
Series7002
LockedYes
Frequency2,800 MHz
Turbo Frequency3,200 MHz
Clock multiplier28
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen 2
Core NameRome
Core Family23
Process7 nm, 14 nm
TechnologyCMOS
MCPYes (3 dies)
Word Size64 bit
Cores8
Threads16
Max Memory4 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP120 W
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm × 58.5 mm × 6.26 mm
Pitch0.87 mm × 1 mm
Contacts4094
SocketSP3, LGA-4094
Succession

EPYC 7252 is a 64-bit octa-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a boost frequency of up to 3.2 GHz. This processor supports up to two-way SMP and up to 4 TiB of eight channels DDR4-3200 memory per socket.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  4x16 MiB  
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7252&oldid=93038"
Facts about "EPYC 7252 - AMD"
RDF feed
base frequency2,800 MHz (2.8 GHz, 2,800,000 kHz) +
clock multiplier28 +
core count8 +
core family23 +
core nameRome +
designerAMD +
die count3 +
familyEPYC +
first announcedAugust 7, 2019 +
first launchedAugust 7, 2019 +
full page nameamd/epyc/7252 +
has locked clock multipliertrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldateAugust 7, 2019 +
manufacturerTSMC + and GlobalFoundries +
market segmentServer +
max cpu count2 +
max memory4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
microarchitectureZen 2 +
model number7252 +
nameEPYC 7252 +
packageSP3 + and FCLGA-4094 +
part number100-000000080 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
series7002 +
smp max ways2 +
socketSP3 + and LGA-4094 +
tdp120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technologyCMOS +
thread count16 +
turbo frequency3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +