Difference between revisions of "intel/xeon w/w-2125"

	Edit Values
	Xeon W-2125
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	W-2125
Part Number	CD8067303533303
S-Spec	SR3LM
Market	Workstation
Introduction	August 29, 2017 (announced); August 29, 2017 (launched)
Release Price	$444.00 (tray)
Shop	Amazon
	General Specs
Family	Xeon W
Series	W-2000
Locked	Yes
Frequency	4,000 MHz
Turbo Frequency	4,500 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	40
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Basin Falls
Core Name	Skylake W
Core Family	6
Core Stepping	U0
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	4
Threads	8
Max Memory	512 GiB
	Multiprocessing
Max SMP	1-Way (Uniprocessor)
	Electrical
TDP	120 W
Tcase	0 °C – 64 °C
	Packaging
Package	FCLGA-2066 (LGA)
Dimension	52.5 mm × 45 mm
Pitch	1.016 mm
Contacts	2066
Socket	Socket R4

Latest revision as of 16:03, 14 May 2019

W-2125 is a 64-bit quad-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 4 GHz with a TDP of 120 W and a turbo boost frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.

Cache[edit]

Main article: Skylake § Cache

Note that while this is a quad-core part, the L3 cache size is that of a hexa-core part.

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

256 KiB

262,144 B
0.25 MiB

L1I$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative
L1D$	128 KiB 131,072 B 0.125 MiB	4x32 KiB	8-way set associative	write-back

L2$

4 MiB

4,096 KiB
4,194,304 B
0.00391 GiB

		4x1 MiB	16-way set associative	write-back

L3$

8.25 MiB

8,448 KiB
8,650,752 B
0.00806 GiB

		6x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	512 GiB
Controllers	2
Channels	4
Max Bandwidth	79.47 GiB/s 81,377.28 MiB/s 85.33 GB/s 85,330.263 MB/s 0.0776 TiB/s 0.0853 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s
Physical Address (PAE)	46 bit

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 48
	Configuration: x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit (2 Units)
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
MPX	Memory Protection Extensions
Secure Key	Secure Key Technology
SMEP	OS Guard Technology
VMD	Volume Management Device
IPT	Identity Protection Technology

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4
Normal	4,000 MHz	4,500 MHz	4,500 MHz	4,400 MHz	4,400 MHz
AVX2		4,000 MHz	4,000 MHz	4,000 MHz	4,000 MHz
AVX512		4,000 MHz	4,000 MHz	3,900 MHz	3,900 MHz

@@ Line 1: / Line 1: @@
 {{intel title|Xeon W-2125}}
-{{mpu
+{{chip
-|future=Yes
 |name=Xeon W-2125
 |image=intel skylake w (front).png
@@ Line 12: / Line 11: @@
 |first announced=August 29, 2017
 |first launched=August 29, 2017
-|release price=$444.00
+|release price (tray)=$444.00
 |family=Xeon W
 |series=W-2000
@@ Line 25: / Line 24: @@
 |isa family=x86
 |microarch=Skylake (server)
-|platform=Purley
+|platform=Basin Falls
 |core name=Skylake W
 |core family=6
@@ Line 37: / Line 36: @@
 |max memory=512 GiB
 |tdp=120 W
-|package module 1={{packages/intel/fclga-2066}}
+|tcase min=0 °C
+|tcase max=64 °C
+|package name 1=intel,fclga_2066
 }}
 '''W-2125''' is a {{arch|64}} [[quad-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2017]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake}} server microarchitecture, operates at 4 GHz with a [[TDP]] of 120 W and a {{intel|turbo boost}} frequency of up to 4.5 GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.
@@ Line 183: / Line 184: @@
 |sensemi=No
 |xfr=No
+}}
+== Frequencies ==
+{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
+{{frequency table
+|freq_base=4,000 MHz
+|freq_1=4,500 MHz
+|freq_2=4,500 MHz
+|freq_3=4,400 MHz
+|freq_4=4,400 MHz
+|freq_avx2_1=4,000 MHz
+|freq_avx2_2=4,000 MHz
+|freq_avx2_3=4,000 MHz
+|freq_avx2_4=4,000 MHz
+|freq_avx512_1=4,000 MHz
+|freq_avx512_2=4,000 MHz
+|freq_avx512_3=3,900 MHz
+|freq_avx512_4=3,900 MHz
 }}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon W-2125 - Intel#pcie +
base frequency	4,000 MHz (4 GHz, 4,000,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
clock multiplier	40 +
core count	4 +
core family	6 +
core name	Skylake W +
core stepping	U0 +
designer	Intel +
family	Xeon W +
first announced	August 29, 2017 +
first launched	August 29, 2017 +
full page name	intel/xeon w/w-2125 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology +
has intel enhanced speedstep technology	true +
has intel identity protection technology support	true +
has intel secure key technology	true +
has intel speed shift technology	true +
has intel supervisor mode execution protection	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	256 KiB (262,144 B, 0.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	128 KiB (131,072 B, 0.125 MiB) +
l1i$ description	8-way set associative +
l1i$ size	128 KiB (131,072 B, 0.125 MiB) +
l2$ description	16-way set associative +
l2$ size	4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description	11-way set associative +
l3$ size	8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) +
ldate	August 29, 2017 +
main image	+
manufacturer	Intel +
market segment	Workstation +
max case temperature	337.15 K (64 °C, 147.2 °F, 606.87 °R) +
max cpu count	1 +
max memory	524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth	79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels	4 +
microarchitecture	Skylake (server) +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	W-2125 +
name	Xeon W-2125 +
number of avx-512 execution units	2 +
package	FCLGA-2066 +
part number	CD8067303533303 +
platform	Basin Falls +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 444.00 (€ 399.60, £ 359.64, ¥ 45,878.52) +
release price (tray)	$ 444.00 (€ 399.60, £ 359.64, ¥ 45,878.52) +
s-spec	SR3LM +
series	W-2000 +
smp max ways	1 +
socket	Socket R4 +
supported memory type	DDR4-2666 +
tdp	120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technology	CMOS +
thread count	8 +
turbo frequency (1 core)	4,500 MHz (4.5 GHz, 4,500,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensions	true +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas