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Difference between revisions of "intel/xeon gold/5218"
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| − | '''Xeon Gold 5218''' is a {{arch|64}} [[16-core]] [[x86]] | + | '''Xeon Gold 5218''' is a {{arch|64}} [[16-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5218 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.3 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 3.9 GHz. |
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== Cache == | == Cache == | ||
Revision as of 23:28, 3 April 2019
| Edit Values | |
| Xeon Gold 5218 | |
| General Info | |
| Designer | Intel |
| Manufacturer | Intel |
| Model Number | 5218 |
| Market | Server |
| Introduction | March, 2019 (announced) March, 2019 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Xeon Gold |
| Series | 5000 |
| Locked | Yes |
| Frequency | 2,300 MHz |
| Turbo Frequency | 3,900 MHz (1 core) |
| Clock multiplier | 23 |
| CPUID | 0x50654 |
| Microarchitecture | |
| ISA | x86-64 (x86) |
| Microarchitecture | Cascade Lake |
| Platform | Purley |
| Chipset | Lewisburg |
| Core Name | Cascade Lake SP |
| Core Family | 6 |
| Process | 14 nm |
| Technology | CMOS |
| Word Size | 64 bit |
| Cores | 16 |
| Threads | 32 |
| Multiprocessing | |
| Max SMP | 4-Way (Multiprocessor) |
| Electrical | |
| TDP | 105 W |
| Tcase | 0 °C – 81 °C |
| TDTS | 0 °C – 93 °C |
| Packaging | |
| Template:packages/intel/fclga-3647 | |
Xeon Gold 5218 is a 64-bit 16-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5218 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as three UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.3 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.9 GHz.
Contents
Cache
- Main article: Cascade Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options
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Features
[Edit/Modify Supported Features]
Facts about "Xeon Gold 5218 - Intel"
| Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 5218 - Intel#io + |
| base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
| chipset | Lewisburg + |
| clock multiplier | 23 + |
| core count | 16 + |
| core family | 6 + |
| core name | Cascade Lake SP + |
| cpuid | 0x50654 + |
| designer | Intel + |
| family | Xeon Gold + |
| first announced | March 2019 + |
| first launched | March 2019 + |
| full page name | intel/xeon gold/5218 + |
| has advanced vector extensions | true + |
| has advanced vector extensions 2 | true + |
| has advanced vector extensions 512 | true + |
| has ecc memory support | true + |
| has extended page tables support | true + |
| has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions + |
| has intel enhanced speedstep technology | true + |
| has intel speed shift technology | true + |
| has intel trusted execution technology | true + |
| has intel turbo boost technology 2 0 | true + |
| has intel vpro technology | true + |
| has intel vt-x technology | true + |
| has locked clock multiplier | true + |
| has second level address translation support | true + |
| has simultaneous multithreading | true + |
| has transactional synchronization extensions | true + |
| has x86 advanced encryption standard instruction set extension | true + |
| instance of | microprocessor + |
| isa | x86-64 + |
| isa family | x86 + |
| l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
| l1d$ description | 8-way set associative + |
| l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l1i$ description | 8-way set associative + |
| l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
| l2$ description | 16-way set associative + |
| l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
| l3$ description | 11-way set associative + |
| l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
| ldate | March 2019 + |
| main image | |
| manufacturer | Intel + |
| market segment | Server + |
| max case temperature | 354.15 K (81 °C, 177.8 °F, 637.47 °R) + |
| max cpu count | 4 + |
| max dts temperature | 93 °C + |
| max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
| max memory channels | 6 + |
| max pcie lanes | 48 + |
| microarchitecture | Cascade Lake + |
| min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
| min dts temperature | 0 °C + |
| model number | 5218 + |
| name | Xeon Gold 5218 + |
| platform | Purley + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| series | 5000 + |
| smp max ways | 4 + |
| supported memory type | DDR4-2400 + |
| tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
| technology | CMOS + |
| thread count | 32 + |
| turbo frequency (1 core) | 3,900 MHz (3.9 GHz, 3,900,000 kHz) + |
| word size | 64 bit (8 octets, 16 nibbles) + |