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|isa 2=ARMv8.0 | |isa 2=ARMv8.0 | ||
|isa 2 family=ARM | |isa 2 family=ARM | ||
− | |microarch=Mongoose | + | |microarch=Mongoose 4 |
|microarch 2=Cortex-A75 | |microarch 2=Cortex-A75 | ||
|microarch 3=Cortex-A55 | |microarch 3=Cortex-A55 | ||
− | |core name=Mongoose | + | |core name=Mongoose 4 |
|core name 2=Cortex-A75 | |core name 2=Cortex-A75 | ||
|core name 3=Cortex-A55 | |core name 3=Cortex-A55 | ||
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|predecessor link=samsung/exynos/9810 | |predecessor link=samsung/exynos/9810 | ||
}} | }} | ||
− | '''Exynos 9820''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in early [[2019]]. The processor is fabricated on Samsung's [[8 nm process|8nm]] LPP (Low Power Plus) FinFET process and features [[8 cores]] in a tri-cluster configuration consisting of 2 {{samsung|Mongoose | + | '''Exynos 9820''' is a {{arch|64}} [[octa-core]] [[ARM]] high performance mobile [[system on a chip]] designed by [[Samsung]] and introduced in early [[2019]]. The processor is fabricated on Samsung's [[8 nm process|8nm]] LPP (Low Power Plus) FinFET process and features [[8 cores]] in a tri-cluster configuration consisting of 2 {{samsung|Mongoose 4|l=arch}} [[big cores]] and 2 {{armh|Cortex-A75|l=arch}} [[middle cores]] and 4 Cortex-A55 [[little cores]]. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a {{armh|Mali-G76}} MP12 GPU. The 9820 incorporates an LTE modem supporting cat 20 download and upload. |
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== Cache == | == Cache == | ||
− | {{main|samsung/microarchitectures/m4#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a76#Memory_Hierarchy|l1=Mongoose | + | {{main|samsung/microarchitectures/m4#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a76#Memory_Hierarchy|l1=Mongoose § Cache||l2=Cortex-A76 § Cache}} |
− | For the {{samsung|Mongoose | + | For the {{samsung|Mongoose 4|l=arch}} core cluster: |
{{cache size | {{cache size | ||
|l1 cache= | |l1 cache= |
Revision as of 22:41, 13 January 2019
Edit Values | |
Exynos 9820 | |
General Info | |
Designer | Samsung, ARM Holdings |
Manufacturer | Samsung |
Model Number | 9820 |
Market | Mobile |
Introduction | November 14, 2018 (announced) January, 2019 (launched) |
General Specs | |
Family | Exynos |
Series | Exynos 9 |
Microarchitecture | |
ISA | ARMv8.2 (ARM), ARMv8.0 (ARM) |
Microarchitecture | Mongoose 4, Cortex-A75, Cortex-A55 |
Core Name | Mongoose 4, Cortex-A75, Cortex-A55 |
Process | 8 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Max Memory | 12 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Succession | |
Exynos 9820 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in early 2019. The processor is fabricated on Samsung's 8nm LPP (Low Power Plus) FinFET process and features 8 cores in a tri-cluster configuration consisting of 2 Mongoose 4 big cores and 2 Cortex-A75 middle cores and 4 Cortex-A55 little cores. This chip supports up to 12 GiB of quad-channel 16-bit LPDDR4X-3600 memory and incorporates a Mali-G76 MP12 GPU. The 9820 incorporates an LTE modem supporting cat 20 download and upload.
Contents
Cache
- Main articles: Mongoose § Cache and Cortex-A76 § Cache
For the Mongoose 4 core cluster:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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For the Cortex-A75 cluster:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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For the Cortex-A55 cluster:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Graphics
Integrated Graphics Information
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Codec | Encode | Decode |
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HEVC (H.265) | ✔ | ✔ |
MPEG-4 AVC (H.264) | ✔ | ✔ |
VP9 | ✔ | ✔ |
All at 4K UHD 150fps.
Wireless
Wireless Communications | |||||||
Cellular | |||||||
4G |
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ISP
- 24MP Rear
- 24MP Front
- 16MP+16MP Dual
Features
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Utilizing devices
- Samsung Galaxy S10
This list is incomplete; you can help by expanding it.
Documents
- all microprocessor models
- microprocessor models by samsung
- microprocessor models by samsung based on mongoose 4
- microprocessor models by samsung based on cortex-a75
- microprocessor models by samsung based on cortex-a55
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on mongoose 4
- microprocessor models by arm holdings based on cortex-a75
- microprocessor models by arm holdings based on cortex-a55
- microprocessor models require attention