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Difference between revisions of "intel/xeon w/w-3175x"
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Revision as of 09:19, 11 October 2018
Edit Values | |
Xeon W-3175X | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | W-3175X |
Market | Workstation |
Introduction | October 8, 2018 (announced) October 19, 2018 (launched) |
Shop | Amazon |
General Specs | |
Family | Xeon W |
Series | W-3000 |
Locked | No |
Frequency | 3,100 MHz |
Turbo Frequency | 4,300 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 31 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Basin Falls |
Core Name | Skylake W |
Core Family | 6 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 28 |
Threads | 56 |
Max Memory | 512 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 255 W |
W-3175X is a 64-bit 28-core x86 enterprise performance workstation microprocessor introduced by Intel in 2018. This processors, which is fabricated on an enhanced 14nm++ process based on the Skylake server microarchitecture, operates at 3.1 GHz with a TDP of 255 W and a turbo boost frequency of up to 4.3 GHz. This chip supports up to 512 GiB of hexa-channel DDR4-2666 ECC memory.
Contents
Cache
- Main article: Skylake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
Expansion Options |
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Features
[Edit/Modify Supported Features]
Facts about "Xeon W-3175X - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-3175X - Intel#pcie + |
base frequency | 3,100 MHz (3.1 GHz, 3,100,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 31 + |
core count | 28 + |
core family | 6 + |
core name | Skylake W + |
designer | Intel + |
family | Xeon W + |
first announced | October 8, 2018 + |
first launched | October 19, 2018 + |
full page name | intel/xeon w/w-3175x + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | false + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,792 KiB (1,835,008 B, 1.75 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 896 KiB (917,504 B, 0.875 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 28 MiB (28,672 KiB, 29,360,128 B, 0.0273 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 38.5 MiB (39,424 KiB, 40,370,176 B, 0.0376 GiB) + |
ldate | 3000 + |
manufacturer | Intel + |
market segment | Workstation + |
max cpu count | 1 + |
max memory | 524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) + |
max memory bandwidth | 119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) + |
max memory channels | 6 + |
microarchitecture | Skylake (server) + |
model number | W-3175X + |
name | Xeon W-3175X + |
number of avx-512 execution units | 2 + |
platform | Basin Falls + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
series | W-3000 + |
smp max ways | 1 + |
supported memory type | DDR4-2666 + |
tdp | 255 W (255,000 mW, 0.342 hp, 0.255 kW) + |
technology | CMOS + |
thread count | 56 + |
turbo frequency (1 core) | 4,300 MHz (4.3 GHz, 4,300,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |