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'''Storm''' is [[AppliedMicro]] first custom [[ARM]] microarchitecture for servers. Storm-based microprocessors were sold under the {{apm|X-Gene 1}} brand of server microprocessors.
 
'''Storm''' is [[AppliedMicro]] first custom [[ARM]] microarchitecture for servers. Storm-based microprocessors were sold under the {{apm|X-Gene 1}} brand of server microprocessors.
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== Codenames ==
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{| class="wikitable"
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|-
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! Codename !! Description
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|-
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| Potenza || codename for the core and memory sub-system
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|}
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== Technology ==
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Storm is fabricated on TSMC's [[40 nm]] bluk CMOS.
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== Architecture ==
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=== Memory Hierarchy ===
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* Cache
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** L1I
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*** 32 KiB, 8-way set associative
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**** Per core
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*** ECC and Parity protection
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** L1D
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*** 32 KiB, 8-way set associative
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**** Per core
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*** 64 B/line
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*** Write-through with [[write-combining]]
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*** ECC and Parity protection
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** L2
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*** 256 KB
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**** Per process module (2 cores)
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***  Inclusive of L1 write-thru data caches
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*** 64 B/line
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*** ECC and Parity protection
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** L3
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*** 8 MiB
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*** 64 B/line
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*** Per chip
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== Die ==
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=== Complete SoC ===
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* [[40 nm process]]
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:[[File:apm storm die.png|600px]]
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:[[File:apm storm die (annotated).png|600px]]
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=== Compute Complex ===
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* 4 PMDs
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:[[File:apm storm potenza complex.png|700px]]
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=== Potenza Processor Module (PMD) ===
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* 2 cores per module
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* shared L2
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* [[40 nm process]]
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* 84,000,000 transistors
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* 14.8 mm² die size
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:[[File:apm storm module.png|700px]]
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:[[File:apm storm module (annotated).png|700px]]
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== Bibliography ==
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* Paramesh Gopi, Gaurav Singh, Greg Favor. ''"X-Gene: 64-bit ARM CPU and SoC."'' Hot Chips 24 Symposium (HCS), 2012 IEEE. IEEE, 2012.
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* Alfred Yeung, et al. (February, 2014). ''"A 3GHz 64b ARM v8 Processor in 40nm Bulk CMOS Technology"''.

Latest revision as of 03:17, 26 September 2018

Edit Values
Storm µarch
General Info
Arch TypeCPU
DesignerAppliedMicro
ManufacturerTSMC
Introduction2011
Process40 nm
Core Configs8
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAARMv8
Succession

Storm is AppliedMicro first custom ARM microarchitecture for servers. Storm-based microprocessors were sold under the X-Gene 1 brand of server microprocessors.

Codenames[edit]

Codename Description
Potenza codename for the core and memory sub-system

Technology[edit]

Storm is fabricated on TSMC's 40 nm bluk CMOS.

Architecture[edit]

Memory Hierarchy[edit]

  • Cache
    • L1I
      • 32 KiB, 8-way set associative
        • Per core
      • ECC and Parity protection
    • L1D
      • 32 KiB, 8-way set associative
        • Per core
      • 64 B/line
      • Write-through with write-combining
      • ECC and Parity protection
    • L2
      • 256 KB
        • Per process module (2 cores)
      • Inclusive of L1 write-thru data caches
      • 64 B/line
      • ECC and Parity protection
    • L3
      • 8 MiB
      • 64 B/line
      • Per chip

Die[edit]

Complete SoC[edit]


apm storm die.png


apm storm die (annotated).png

Compute Complex[edit]

  • 4 PMDs
apm storm potenza complex.png

Potenza Processor Module (PMD)[edit]

  • 2 cores per module
  • shared L2
  • 40 nm process
  • 84,000,000 transistors
  • 14.8 mm² die size
apm storm module.png
apm storm module (annotated).png

Bibliography[edit]

  • Paramesh Gopi, Gaurav Singh, Greg Favor. "X-Gene: 64-bit ARM CPU and SoC." Hot Chips 24 Symposium (HCS), 2012 IEEE. IEEE, 2012.
  • Alfred Yeung, et al. (February, 2014). "A 3GHz 64b ARM v8 Processor in 40nm Bulk CMOS Technology".
Retrieved from "https://en.wikichip.org/w/index.php?title=apm/microarchitectures/storm&oldid=82888"
Facts about "Storm - Microarchitectures - AppliedMicro"
RDF feed
codenameStorm +
core count8 +
designerAppliedMicro +
first launched2011 +
full page nameapm/microarchitectures/storm +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameStorm +
process40 nm (0.04 μm, 4.0e-5 mm) +