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{| class="wikitable" | {| class="wikitable" | ||
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− | ! Core !! Target | + | ! Core !! Abbrev !! Target |
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− | | {{intel|Cascade Lake X|l=core}} || High-end desktops & enthusiasts market | + | | {{intel|Cascade Lake X|l=core}} || CLX-X || High-end desktops & enthusiasts market |
|- | |- | ||
− | | {{intel|Cascade Lake W|l=core}} || Enterprise/Business workstations | + | | {{intel|Cascade Lake W|l=core}} || CLX-W || Enterprise/Business workstations |
|- | |- | ||
− | | {{intel|Cascade Lake SP|l=core}} || Server Scalable Processors | + | | {{intel|Cascade Lake SP|l=core}} || CLX-SP || Server Scalable Processors |
+ | |- | ||
+ | | {{intel|Cascade Lake AP|l=core}} || CLX-AP || Server Advanced Processors | ||
|} | |} | ||
Revision as of 13:36, 9 June 2018
Edit Values | |
Cascade Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | 2018 |
Process | 14 nm |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512 |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L2 Cache | 1 MiB/core 16-way set associative |
L3 Cache | 1.375 MiB/core 11-way set associative |
Cores | |
Core Names | Cascade Lake X, Cascade Lake SP |
Succession | |
Contemporary | |
Coffee Lake |
Cascade Lake (CLX) Server Configuration is Intel's successor to Skylake, a 14 nm microarchitecture for enthusiasts and servers. Cascade Lake is the "Optimization" phase as part of Intel's PAO model.
For desktop enthusiasts, Cascade Lake is branded Core i7, and Core i9 processors (under the Core X series). For scalable server class processors, Intel branded it as Xeon Bronze, Xeon Silver, Xeon Gold, and Xeon Platinum.
Contents
Codenames
Core | Abbrev | Target |
---|---|---|
Cascade Lake X | CLX-X | High-end desktops & enthusiasts market |
Cascade Lake W | CLX-W | Enterprise/Business workstations |
Cascade Lake SP | CLX-SP | Server Scalable Processors |
Cascade Lake AP | CLX-AP | Server Advanced Processors |
Brands
Cascade Lake is sold under eight different families.
Logo | Family | General Description | Differentiating Features | ||||||
---|---|---|---|---|---|---|---|---|---|
Cores | HT | AVX | AVX2 | AVX-512 | TBT | ECC | |||
Core i7 | Enthusiasts/High Performance (X) | ?-? | ✔ | ✔ | ✔ | ✔ | ✔ | ✘ | |
Core i9 | Enthusiasts/High Performance | 10 - 28 | ✔ | ✔ | ✔ | ✔ | ✔ | ✘ | |
Logo | Family | General Description | Differentiating Features | ||||||
Cores | HT | TBT | AVX-512 | AVX-512 Units | UPI links | Scalability | |||
Xeon D | Dense servers / edge computing | 4-18 | ✔ | ✔ | ✔ | 1 | ✘ | ||
Xeon W | Business workstations | 4-18 | ✔ | ✔ | ✔ | 2 | ✘ | ||
Xeon Bronze | Entry-level performance / Cost-sensitive |
6 - 8 | ✘ | ✘ | ✔ | 1 | 2 | Up to 2 | |
Xeon Silver | Mid-range performance / Efficient lower power |
4 - 12 | ✔ | ✔ | ✔ | 1 | 2 | Up to 2 | |
Xeon Gold 5000 | High performance | 4 - 14 | ✔ | ✔ | ✔ | 1 | 2 | Up to 4 | |
Xeon Gold 6000 | Higher performance | 6 - 22 | ✔ | ✔ | ✔ | 2 | 3 | Up to 4 | |
Xeon Platinum | Highest performance / flexibility | 4 - 28 | ✔ | ✔ | ✔ | 2 | 3 | Up to 8 |
Release Dates
Cascade Lake is expected to be released in mid-2018.
Process Technology
Cascade Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.
Architecture
As with Skylake, Cascade Lake is also based on the Purley platform and is designed as a drop-in upgrade.
Key changes from Skylake
- Architectural improvements (specifics unknown yet)
- Core
- Security
- Fix for CVE-2017-5715 (Spectre, Variant 2)
- Fix for CVE-2017-5754 (Meltdown, Variant 3)
- Security
- Package
- Selected SKUs with Arria 10 FPGAs in a MCP
- Memory
- 2933 MT/s DDR4 (up from 2666 MT/s)
- Support for DDR-T / Optane DIMMs
This list is incomplete; you can help by expanding it.
New instructions
Cascade Lake introduced a number of new instructions:
-
AVX-512 VNNI
- AVX-512 Vector Neural Network Instructions
Block Diagram
This section is empty; you can help add the missing info by editing this page. |
codename | Cascade Lake + |
designer | Intel + |
first launched | 2018 + |
full page name | intel/microarchitectures/cascade lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cascade Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |