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Difference between revisions of "intel/xeon"
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| style="background-color: #ebebe0;" | {{intel|Haswell EX|l=core}} || style="background-color: #eeffcc;" | 8,10,12,14,16,18 | | style="background-color: #ebebe0;" | {{intel|Haswell EX|l=core}} || style="background-color: #eeffcc;" | 8,10,12,14,16,18 | ||
|- style="height: 25px;" | |- style="height: 25px;" | ||
− | | style="background-color: #ffe6ff;" rowspan=" | + | | style="background-color: #ffe6ff;" rowspan="8" | [[14 nm]] || style="background-color: #b3ffb3;" rowspan="2" | {{intel|Broadwell|l=arch}} || style="background-color: #ebebe0;" | {{intel|Broadwell DE|l=core}} || style="background-color: #eeffcc;" | 4,6,8,12,16 |
|- style="height: 25px;" | |- style="height: 25px;" | ||
| style="background-color: #ebebe0;" | {{intel|Broadwell H|l=core}} || style="background-color: #eeffcc;" | 4 | | style="background-color: #ebebe0;" | {{intel|Broadwell H|l=core}} || style="background-color: #eeffcc;" | 4 | ||
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|style="background-color: #b3ffb3;" | {{intel|Skylake|l=arch}} || style="background-color: #ebebe0;" | {{intel|Skylake H|l=core}} || style="background-color: #eeffcc;" | 4 | |style="background-color: #b3ffb3;" | {{intel|Skylake|l=arch}} || style="background-color: #ebebe0;" | {{intel|Skylake H|l=core}} || style="background-color: #eeffcc;" | 4 | ||
+ | |- style="height: 25px;" | ||
+ | | style="background-color: #e6f7ff;" | 2017 || style="background-color: #fff5cc;" rowspan="2" | {{intel|Xeon Bronze}}<br>{{intel|Xeon Silver}}<br>{{intel|Xeon Gold}}<br>{{intel|Xeon Platinum}} || style="background-color: #b3ffb3;" | {{intel|Skylake (Server)|l=arch}} || style="background-color: #ebebe0;" | {{intel|Skylake SP|l=core}} || style="background-color: #eeffcc;" | 4,6,8,10,12,14,16,18,20,22,24,26,28 | ||
+ | |- style="height: 25px;" | ||
+ | | style="background-color: #e6f7ff;" | 2018 || style="background-color: #b3ffb3;" | {{intel|Cascade Lake|l=arch}} || style="background-color: #ebebe0;" | {{intel|Cascade Lake SP|l=core}} || style="background-color: #eeffcc;" | 4,6,8,10,12,14,16,18,20,22,24,26,28 | ||
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Revision as of 15:11, 27 March 2018
Xeon | |
Past and current logos | |
Developer | Intel |
Manufacturer | Intel |
Type | Microprocessors |
Introduction | June 29, 1998 (announced) 1998 (launch) |
Production | 1998 |
ISA | x86-64 |
µarch | P6, NetBurst, Core, Penryn, Nehalem, Westmere, Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake |
Word size | 32 bit 4 octets , 64 bit8 nibbles 8 octets
16 nibbles |
Process | 350 nm 0.35 μm , 250 nm3.5e-4 mm 0.25 μm , 180 nm2.5e-4 mm 0.18 μm , 65 nm1.8e-4 mm 0.065 μm , 45 nm6.5e-5 mm 0.045 μm , 32 nm4.5e-5 mm 0.032 μm , 22 nm3.2e-5 mm 0.022 μm , 14 nm2.2e-5 mm 0.014 μm
1.4e-5 mm |
Technology | CMOS |
Clock | 400 MHz-4000 MHz |
Succession | |
← | |
Pentium Pro |
Xeon (pronounced "Zee-On") is an extended family of high-performance x86 microprocessors developed by Intel for server environments and non-consumer workstations. Over the years Xeon has grown to focus on high-bandwidth, large-memory, and highly concurrent workloads. Xeon processors typically incorporate a large number of cores, large cache, and support for large amount of memory. Xeon offers models for both uniprocessor or multiprocessors.
Xeon Timeline
See also
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |
Facts about "Xeon - Intel"
designer | Intel + |
first announced | June 29, 1998 + |
first launched | 1998 + |
full page name | intel/xeon + |
instance of | microprocessor extended family + |
instruction set architecture | x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | P6 +, NetBurst +, Core +, Penryn +, Nehalem +, Westmere +, Sandy Bridge +, Ivy Bridge +, Haswell +, Broadwell + and Skylake + |
name | Xeon + |
process | 350 nm (0.35 μm, 3.5e-4 mm) +, 250 nm (0.25 μm, 2.5e-4 mm) +, 180 nm (0.18 μm, 1.8e-4 mm) +, 65 nm (0.065 μm, 6.5e-5 mm) +, 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) + |