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Difference between revisions of "zhaoxin/microarchitectures/wudaokou"
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** New [[Uncore]] | ** New [[Uncore]] | ||
*** [[northbridge]] moved on-die | *** [[northbridge]] moved on-die | ||
− | *** PCIe 3.0 (from 2.0) | + | *** [[PCIe]] 3.0 (from 2.0) |
+ | *** [[DDR4]] (From [[DDR3]]) | ||
+ | ** New integrated graphics processor | ||
+ | * [[FSB]] removed | ||
+ | ** x4 PCIe 3.0 communication with [[southbridge]] chipset | ||
{{empty section}} | {{empty section}} |
Revision as of 23:52, 14 January 2018
Edit Values | |
WuDaoKou µarch | |
General Info | |
Arch Type | CPU |
Designer | Zhaoxin |
Manufacturer | HLMC |
Introduction | December 28, 2017 |
Process | 28 nm |
Core Configs | 2, 4, 8 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Instructions | |
ISA | x86-64 |
Succession | |
WuDaoKou is the successor to Zhangjiang, a 28 nm x86 microarchitecture designed by Zhaoxin for mainstream laptops, desktops, and servers.
Brands
Family | Series | Description |
---|---|---|
KaiXian | KX (5000) | Desktop, Laptops |
Kaisheng | KH (20000) | Storage, Servers |
Process Technology
WuDaoKou is manufactured on HLMC's 28 nm process.
Architecture
Key changes from Zhangjiang
- 8 cores per die (up from 4)
- SoC design
- New Uncore
- northbridge moved on-die
- PCIe 3.0 (from 2.0)
- DDR4 (From DDR3)
- New integrated graphics processor
- New Uncore
- FSB removed
- x4 PCIe 3.0 communication with southbridge chipset
This section is empty; you can help add the missing info by editing this page. |
Facts about "WuDaoKou - Microarchitectures - Zhaoxin"
codename | WuDaoKou + |
core count | 2 +, 4 + and 8 + |
designer | Zhaoxin + |
first launched | December 28, 2017 + |
full page name | zhaoxin/microarchitectures/wudaokou + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | HLMC + |
microarchitecture type | CPU + |
name | WuDaoKou + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |