Semiconductor & Computer Engineering
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== Families == | == Families == | ||
| − | + | === Bonnell === | |
| + | {{main|intel/microarchitectures/bonnell|l1=Bonnel Microarchitecture}} | ||
| + | '''Bonnell''' was the first microarchitecture designed specifically for the ultra-low power microprocessor market. Introduced in 2008, it featured fully [[x86]]-compatible cores with a TDP of only 500 mW to 2 W, less than any other x86 processor available that the time. All Bonnell-based processors were manufactured on Intel's [[45 nm process]]. | ||
| + | |||
| + | ==== Silverthorne Core ==== | ||
| + | [[File:intel atom logo (2008-2009).png|right|200px]] | ||
| + | {{main|intel/cores/silverthorne|l1=Silverthorne Core}} | ||
| + | The first series of Bonnell processors were introduced during the [[2008]] Intel Developer Forum (IDF) in Shanghai, China. Those {{arch|32}} processors were based on the the {{intel|Silverthorne|l=core}} core which were designed for the [[Mobile Internet Devices]] (MID) market. Silverthorne processors have 56 [[KiB]] of L1$ and 512 KiB of L2. Silverthorne has support for the traditional [[GTL|AGTL+]]-based [[FSB]] as well as a new low power [[CMOS]] FSB specifically introduced to reduce power. | ||
| + | |||
| + | Silverthorne chips consist of 47 million [[transistors]] on a 4.2 mm² die packaged in a tiny 13mm x 14mm {{intel|FCBGA-437}} and {{intel|PBGA-441}} [[packages]]. All processors are a [[single core]] with {{intel|Hyper-Threading}}. Additionally all models support every [[x86]] extension up to {{intel|SSSE3}} ({{intel|SMM}}, {{intel|FPU}}, {{intel|NX}}, {{intel|MMX}}, {{intel|SSE}}, {{intel|SSE2}}, {{intel|SSE3}}, {{intel|SSSE3}}). | ||
| + | <!-- | ||
=== Microprocessors === | === Microprocessors === | ||
* {{intel|Atom 230|Atom 230 Series}}, 2008 | * {{intel|Atom 230|Atom 230 Series}}, 2008 | ||
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=== System on a chip === | === System on a chip === | ||
* {{intel|Atom Z2000|Atom Z2000 Series}}, 2012 | * {{intel|Atom Z2000|Atom Z2000 Series}}, 2012 | ||
| − | * {{intel|Atom Z3000|Atom Z3000 Series}}, 2013 | + | * {{intel|Atom Z3000|Atom Z3000 Series}}, 2013--> |
| + | === SoCs === | ||
* {{intel|Atom x3}}, 2015 | * {{intel|Atom x3}}, 2015 | ||
* {{intel|Atom x5}}, 2015 | * {{intel|Atom x5}}, 2015 | ||
Revision as of 02:01, 30 March 2017
| Intel Atom | |
.png)
| |
| Intel Atom (2015 logo) | |
| Developer | Intel |
| Manufacturer | Intel |
| Type | system on chips, microprocessors |
| Introduction | March 2, 2008 (announced) April 2, 2008 (launch) |
| ISA | IA-32, x86-64 |
| Word size | 32 32 bit , 644 octets 8 nibbles 64 bit
8 octets 16 nibbles |
| Process | 45 nm 0.045 μm , 32 nm4.5e-5 mm 0.032 μm , 22 nm3.2e-5 mm 0.022 μm , 14 nm2.2e-5 mm 0.014 μm
1.4e-5 mm |
| Technology | CMOS |
| Clock | 500 MHz-2400 MHz |
| Socket | BGA |
Atom is an extended family of ultra-low-voltage 32 and 64-bit microprocessors and system on chips designed by Intel.
Families
Bonnell
- Main article: Bonnel Microarchitecture
Bonnell was the first microarchitecture designed specifically for the ultra-low power microprocessor market. Introduced in 2008, it featured fully x86-compatible cores with a TDP of only 500 mW to 2 W, less than any other x86 processor available that the time. All Bonnell-based processors were manufactured on Intel's 45 nm process.
Silverthorne Core
.png){kind=logo}
- Main article: Silverthorne Core
The first series of Bonnell processors were introduced during the 2008 Intel Developer Forum (IDF) in Shanghai, China. Those 32-bit processors were based on the the Silverthorne core which were designed for the Mobile Internet Devices (MID) market. Silverthorne processors have 56 KiB of L1$ and 512 KiB of L2. Silverthorne has support for the traditional AGTL+-based FSB as well as a new low power CMOS FSB specifically introduced to reduce power.
Silverthorne chips consist of 47 million transistors on a 4.2 mm² die packaged in a tiny 13mm x 14mm FCBGA-437 and PBGA-441 packages. All processors are a single core with Hyper-Threading. Additionally all models support every x86 extension up to SSSE3 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3).
SoCs
Microarchitectures
| T/T | Process | µarch | Intro Date | Cores |
|---|---|---|---|---|
| Tick | 45 nm | Bonnell | 2008 | Silverthorne, Diamondville |
| Tock | 2010 | Lincroft, Pineview, Tunnel Creek, Stellarton, Sodaville, Groveland | ||
| Tick | 32 nm | Saltwell | 2011 | Clover Trail, Cedar Trail |
| Tick | 22 nm | Silvermont | 2013 | Bay Trail |
| Tock | 14 nm | Airmont | 2015 | Cherry Trail, Braswell |
| Tick | Goldmont | 2016 |
Features
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This section is empty; you can help add the missing info by editing this page. |
 |
This article is still a stub and needs your attention. You can help improve this article by editing this page and adding the missing information. |
| designer | Intel + |
| first announced | March 2, 2008 + |
| first launched | April 2, 2008 + |
| full page name | intel/atom + |
| instance of | system on a chip extended family + and microprocessor extended family + |
| instruction set architecture | IA-32 + and x86-64 + |
| main designer | Intel + |
| manufacturer | Intel + |
| name | Intel Atom + |
| process | 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
| socket | BGA + |
| technology | CMOS + |
| word size | 32 bit (4 octets, 8 nibbles) + and 64 bit (8 octets, 16 nibbles) + |