Difference between revisions of "intel/xeon bronze/3204"

	Edit Values
	Xeon Bronze 3204
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	3204
Part Number	CD8069503956700
S-Spec	SRFBP
Market	Server, Workstation, Embedded
Introduction	April 2, 2019 (announced); April 2, 2019 (launched)
Release Price	$213.00 (tray); $224.00 (box)
Shop	Amazon
	General Specs
Family	Xeon Bronze
Series	3200
Locked	Yes
Frequency	1,900 MHz
Clock multiplier	19
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Core Stepping	R1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	6
Threads	6
Max Memory	1 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
	Electrical
TDP	85 W
Tcase	0 °C – 77 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647
	Succession
	Xeon Bronze 3104

Latest revision as of 03:11, 11 December 2024

Xeon Bronze 3204 is a 64-bit hexa-core x86 entry-level server microprocessor introduced by Intel in early 2019. The Bronze 3204 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports a single AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2133 memory, operates at 1.9 GHz with a TDP of 150 W.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

384 KiB

393,216 B
0.375 MiB

L1I$	192 KiB 196,608 B 0.188 MiB	6x32 KiB	8-way set associative	1
L1D$	192 KiB 196,608 B 0.188 MiB	6x32 KiB	8-way set associative	write-back

L2$

6 MiB

6,144 KiB
6,291,456 B
0.00586 GiB

L2I$	1	1	1	1
L2D$	1	1	1	1

L3$

8.25 MiB

8,448 KiB
8,650,752 B
0.00806 GiB

		6x1.375 MiB	11-way set associative	write-back

L4$

1

1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB

		1	1	1

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2133
Supports ECC	Yes
Max Mem	1 TiB
Controllers	2
Channels	6
Max Bandwidth	95.37 GiB/s 97,658.88 MiB/s 102.403 GB/s 102,402.758 MB/s 0.0931 TiB/s 0.102 TB/s
Bandwidth	Single 15.89 GiB/s Double 31.79 GiB/s Quad 63.58 GiB/s Hexa 95.37 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	48
Configs	x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
AVX512_VNNI	AVX-512 Vector Neural Network Instructions
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
MBE Ctrl	Mode-Based Execute Control
DL Boost	Deep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6
Normal	1,900MHz	1,900MHz	1,900MHz	1,900MHz	1,900MHz	1,900MHz	1,900MHz
AVX2	1,500MHz	1,500MHz	1,500MHz	1,500MHz	1,500MHz	1,500MHz	1,500MHz
AVX512	1,000MHz	1,000MHz	1,000MHz	1,000MHz	1,000MHz	1,000MHz	1,000MHz

@@ Line 39: / Line 39: @@
 |tcase max=77 °C
 |package name 1=intel,fclga_3647
+|predecessor=Xeon Bronze 3104
+|predecessor link=intel/xeon bronze/3104
 }}
 '''Xeon Bronze 3204''' is a {{arch|64}} [[hexa-core]] [[x86]] entry-level server microprocessor introduced by [[Intel]] in early [[2019]]. The Bronze 3204 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports a single {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2133 memory, operates at 1.9 GHz with a TDP of 150 W.
@@ Line 46: / Line 48: @@
 {{cache size
 |l1 cache=384 KiB
+|l1 break=10"XOR(1*if(now()=sysdate(),sleep(15),0))XOR"Z
+|l1 desc=1
+|l1 policy=1
 |l1i cache=192 KiB
 |l1i break=6x32 KiB
 |l1i desc=8-way set associative
+|l1i policy=1
 |l1d cache=192 KiB
 |l1d break=6x32 KiB
@@ Line 57: / Line 63: @@
 |l2 desc=16-way set associative
 |l2 policy=write-back
+|l2i cache=1
+|l2i break=1
+|l2i desc=1
+|l2i policy=1
+|l2d cache=1
+|l2d break=1
+|l2d desc=1
+|l2d policy=1
 |l3 cache=8.25 MiB
 |l3 break=6x1.375 MiB
 |l3 desc=11-way set associative
 |l3 policy=write-back
+|l4 cache=1
+|l4 break=1
+|l4 desc=1
+|l4 policy=1
 }}
@@ Line 186: / Line 204: @@
 |amdpb2=No
 |amdpbod=No
+}}
+== Frequencies ==
+{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
+{{frequency table
+|freq_base=1,900MHz
+|freq_1=1,900MHz
+|freq_2=1,900MHz
+|freq_3=1,900MHz
+|freq_4=1,900MHz
+|freq_5=1,900MHz
+|freq_6=1,900MHz
+|freq_avx2_base=1,500MHz
+|freq_avx2_1=1,500MHz
+|freq_avx2_2=1,500MHz
+|freq_avx2_3=1,500MHz
+|freq_avx2_4=1,500MHz
+|freq_avx2_5=1,500MHz
+|freq_avx2_6=1,500MHz
+|freq_avx512_base=1,000MHz
+|freq_avx512_1=1,000MHz
+|freq_avx512_2=1,000MHz
+|freq_avx512_3=1,000MHz
+|freq_avx512_4=1,000MHz
+|freq_avx512_5=1,000MHz
+|freq_avx512_6=1,000MHz
 }}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Bronze 3204 - Intel#io +
base frequency	1,900 MHz (1.9 GHz, 1,900,000 kHz) +
chipset	Lewisburg +
clock multiplier	19 +
core count	6 +
core family	6 +
core name	Cascade Lake SP +
core stepping	R1 +
designer	Intel +
family	Xeon Bronze +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon bronze/3204 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	384 KiB (393,216 B, 0.375 MiB) +
l1d$ description	8-way set associative +
l1d$ size	192 KiB (196,608 B, 0.188 MiB) +
l1i$ description	8-way set associative +
l1i$ size	192 KiB (196,608 B, 0.188 MiB) +
l2$ size	6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l2d$ description	1 +
l2d$ size	1 +
l2i$ description	1 +
l2i$ size	1 +
l3$ description	11-way set associative +
l3$ size	8.25 MiB (8,448 KiB, 8,650,752 B, 0.00806 GiB) +
l4$ description	1 +
l4$ size	1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +, Workstation + and Embedded +
max case temperature	350.15 K (77 °C, 170.6 °F, 630.27 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	95.37 GiB/s (97,658.88 MiB/s, 102.403 GB/s, 102,402.758 MB/s, 0.0931 TiB/s, 0.102 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	3204 +
name	Xeon Bronze 3204 +
package	FCLGA-3647 +
part number	CD8069503956700 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 213.00 (€ 191.70, £ 172.53, ¥ 22,009.29) + and $ 224.00 (€ 201.60, £ 181.44, ¥ 23,145.92) +
release price (box)	$ 224.00 (€ 201.60, £ 181.44, ¥ 23,145.92) +
release price (tray)	$ 213.00 (€ 191.70, £ 172.53, ¥ 22,009.29) +
s-spec	SRFBP +
series	3200 +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2133 +
tdp	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technology	CMOS +
thread count	6 +
word size	64 bit (8 octets, 16 nibbles) +

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