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|type=DDR5-4800 | |type=DDR5-4800 |
Latest revision as of 01:48, 2 April 2023
Edit Values | |
EPYC 9254 | |
General Info | |
Designer | AMD |
Manufacturer | TSMC |
Model Number | 9254 |
Part Number | 100-100000480, 100-100000480WOF |
Market | Server |
Introduction | November 10, 2022 (launched) |
Release Price | $2299.00 (tray) |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 9004 |
Locked | Yes |
Frequency | 2,900 MHz |
Turbo Frequency | 3,900 MHz |
Turbo Frequency | 4,150 MHz (1 core) |
Clock multiplier | 29 |
CPUID | 0x00A10F11 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen 4 |
Core Name | Genoa |
Core Family | 25 |
Core Model | 17 |
Core Stepping | B1 |
Process | 5 nm, 6 nm |
Technology | CMOS |
MCP | Yes (5 dies) |
Word Size | 64 bit |
Cores | 24 |
Threads | 48 |
Max Memory | 6 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 200 W |
cTDP up | 240 W |
Packaging | |
Package | SP5 (FC-OLGA) |
Dimension | 75.4 mm × 72 mm |
Pitch | 0.81 mm × 0.94 mm |
Contacts | 6096 |
Socket | Socket SP5 |
EPYC 9254 is a 64-bit 24-core x86 server microprocessor designed and introduced by AMD in late 2022. This multi-chip processor, which is based on the Zen 4 microarchitecture, incorporates four Core Complex Dies fabricated on a TSMC 5 nm process and a large I/O die also manufactured by TSMC. The 9254 has a TDP of 200 W with a base frequency of 2.9 GHz and a boost frequency of up to 4.15 GHz. This processor supports up to two-way SMP and up to 6 TiB of 12 channel DDR5-4800 memory per socket.
Cache[edit]
- Main article: Zen 4 § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
- Main article: Genoa § Memory Interface
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Integrated Memory Controller
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Note one memory channel comprises two independent DDR5 subchannels with 32 data and 8 ECC lanes each.
Expansions[edit]
- Main article: Genoa § I/O Interfaces
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Expansion Options |
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[Edit/Modify Supported Features]
Bibliography[edit]
- "AMD Processor Specifications". AMD.com. Retrieved February 2023.
- "AMD EPYC™ 9254". AMD.com. Retrieved February 2023.
- "Revision Guide for AMD Family 19h Models 10h-1Fh Processors", AMD Publ. #57095, Rev. 1.00, December 9, 2022
Facts about "EPYC 9254 - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | EPYC 9254 - AMD#pcie + |
base frequency | 2,900 MHz (2.9 GHz, 2,900,000 kHz) + |
clock multiplier | 29 + |
core count | 24 + |
core family | 25 + |
core model | 17 + |
core name | Genoa + |
core stepping | B1 + |
cpuid | 0x00A10F11 + |
designer | AMD + |
die count | 5 + |
family | EPYC + |
first launched | November 10, 2022 + |
full page name | amd/epyc/9254 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd secure encrypted virtualization technology | true + |
has amd secure memory encryption technology | true + |
has amd sensemi technology | true + |
has amd transparent secure memory encryption technology | true + |
has ecc memory support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology + |
has locked clock multiplier | true + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
is multi-chip package | true + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l2$ description | 8-way set associative + |
l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
l3$ description | 16-way set associative + |
l3$ size | 128 MiB (131,072 KiB, 134,217,728 B, 0.125 GiB) + |
ldate | November 10, 2022 + |
manufacturer | TSMC + |
market segment | Server + |
max cpu count | 2 + |
max memory | 6,291,456 MiB (6,442,450,944 KiB, 6,597,069,766,656 B, 6,144 GiB, 6 TiB) + |
max memory bandwidth | 429.153 GiB/s (439,453.125 MiB/s, 460.8 GB/s, 460,800 MB/s, 0.419 TiB/s, 0.461 TB/s) + |
max memory channels | 12 + |
max sata ports | 32 + |
max usb ports | 4 + |
microarchitecture | Zen 4 + |
model number | 9254 + |
name | EPYC 9254 + |
package | SP5 + |
part number | 100-100000480 + and 100-100000480WOF + |
process | 5 nm (0.005 μm, 5.0e-6 mm) + and 6 nm (0.006 μm, 6.0e-6 mm) + |
release price | $ 2,299.00 (€ 2,069.10, £ 1,862.19, ¥ 237,555.67) + |
release price (tray) | $ 2,299.00 (€ 2,069.10, £ 1,862.19, ¥ 237,555.67) + |
series | 9004 + |
smp max ways | 2 + |
socket | Socket SP5 + |
supported memory type | DDR5-4800 + |
tdp | 200 W (200,000 mW, 0.268 hp, 0.2 kW) + |
tdp up | 240 W (240,000 mW, 0.322 hp, 0.24 kW) + |
technology | CMOS + |
thread count | 48 + |
turbo frequency | 3,900 MHz (3.9 GHz, 3,900,000 kHz) + |
turbo frequency (1 core) | 4,150 MHz (4.15 GHz, 4,150,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |