From WikiChip
Exynos 9810 - Samsung
Edit Values | |
Exynos 9810 | |
General Info | |
Designer | Samsung, ARM Holdings |
Manufacturer | Samsung |
Model Number | 9810 |
Market | Mobile |
Introduction | January 3, 2018 (announced) February 25, 2018 (launched) |
General Specs | |
Family | Exynos |
Series | Exynos 9 |
Frequency | 2,704 MHz, 1,794 MHz |
Turbo Frequency | 2,704 MHz |
Turbo Frequency | 2,704 MHz (1 core), 2,314 MHz (2 cores), 1,794 MHz (4 cores) |
Microarchitecture | |
ISA | ARMv8.2 (ARM), ARMv8.0 (ARM) |
Microarchitecture | Exynos M3, Cortex-A55 |
Core Name | Meerkat, Cortex-A55 |
Process | 10 nm |
Technology | CMOS |
Die | 118.94 mm² |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Succession | |
Exynos 9810 is a 64-bit octa-core ARM performance microprocessor designed by Samsung and introduced in 2018 for their consumer electronics. The processor is fabricated on Samsung's 10 nm process and features 8 cores in a configuration consisting of 4 Mongoose 3 big cores operating at 2.7 GHz (Up to 2.9 GHz) and 4 Cortex-A55 little cores operating at 1.8 GHz (Up to 2 GHz). This chip supports up to 8 GiB of quad-channel 16-bit LPDDR4X-3588(MT/s) memory and incorporates a Mali-G72 MP18 GPU operating at 572 MHz. The 9810 incorporates an LTE modem supporting cat 18 download and cat 13 upload.
Cache[edit]
- Main articles: Mongoose 3 § Cache and Cortex-A55 § Cache
For the Mongoose 3 core cluster:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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For the Cortex-A55 cluster:
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Graphics[edit]
Integrated Graphics Information
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Codec | Encode | Decode |
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HEVC (H.265) | ✔ | ✔ |
MPEG-4 AVC (H.264) | ✔ | ✔ |
VP9 | ✔ | ✔ |
All at 4K UHD 120fps.
Wireless[edit]
Wireless Communications | |||||||
Cellular | |||||||
4G |
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ISP[edit]
- 24MP Rear
- 24MP Front
- 16MP+16MP Dual
Features[edit]
[Edit/Modify Supported Features]
Supported ARM Extensions & Processor Features
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Utilizing devices[edit]
- Samsung Galaxy S9
- Samsung Galaxy S9+
- Samsung Galaxy Note 9
- Samsung Galaxy Xcover FieldPro
- Samsung Galaxy Note 10 Lite
- Samsung Galaxy Tab Active3
Categories:
- all microprocessor models
- microprocessor models by samsung
- microprocessor models by samsung based on exynos m3
- microprocessor models by samsung based on cortex-a55
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on exynos m3
- microprocessor models by arm holdings based on cortex-a55
Facts about "Exynos 9810 - Samsung"
base frequency | 2,704 MHz (2.704 GHz, 2,704,000 kHz) + and 1,794 MHz (1.794 GHz, 1,794,000 kHz) + |
core count | 8 + |
core name | Meerkat + and Cortex-A55 + |
designer | Samsung + and ARM Holdings + |
die area | 118.94 mm² (0.184 in², 1.189 cm², 118,940,000 µm²) + |
family | Exynos + |
first announced | January 3, 2018 + |
first launched | February 25, 2018 + |
full page name | samsung/exynos/9810 + |
has 4g support | true + |
has ecc memory support | false + |
has lte advanced support | true + |
instance of | microprocessor + |
integrated gpu | Mali-G72 + |
integrated gpu base frequency | 572 MHz (0.572 GHz, 572,000 KHz) + |
integrated gpu designer | ARM Holdings + |
integrated gpu execution units | 18 + |
integrated gpu max frequency | 598 MHz (0.598 GHz, 598,000 KHz) + |
isa | ARMv8.2 + and ARMv8.0 + |
isa family | ARM + |
l1$ size | 384 KiB (393,216 B, 0.375 MiB) + and 256 KiB (262,144 B, 0.25 MiB) + |
l1d$ description | 8-way set associative + and 4-way set associative + |
l1d$ size | 128 KiB (131,072 B, 0.125 MiB) + |
l1i$ description | 4-way set associative + and 2-way set associative + |
l1i$ size | 256 KiB (262,144 B, 0.25 MiB) + and 128 KiB (131,072 B, 0.125 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) + and 0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) + |
l3$ size | 4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) + |
ldate | February 25, 2018 + |
main image | + |
manufacturer | Samsung + |
market segment | Mobile + |
max cpu count | 1 + |
max memory channels | 2 + |
microarchitecture | Exynos M3 + and Cortex-A55 + |
model number | 9810 + |
name | Exynos 9810 + |
process | 10 nm (0.01 μm, 1.0e-5 mm) + |
series | Exynos 9 + |
smp max ways | 1 + |
supported memory type | LPDDR4X-3588 + |
technology | CMOS + |
thread count | 8 + |
turbo frequency | 2,704 MHz (2.704 GHz, 2,704,000 kHz) + |
turbo frequency (1 core) | 2,704 MHz (2.704 GHz, 2,704,000 kHz) + |
turbo frequency (2 cores) | 2,314 MHz (2.314 GHz, 2,314,000 kHz) + |
turbo frequency (4 cores) | 1,794 MHz (1.794 GHz, 1,794,000 kHz) + |
used by | Samsung Galaxy S9 +, Samsung Galaxy S9+ +, Samsung Galaxy Note 9 +, Samsung Galaxy Xcover FieldPro +, Samsung Galaxy Note 10 Lite + and Samsung Galaxy Tab Active3 + |
user equipment category downlink | 18 + |
user equipment category uplink | 13 + |
word size | 64 bit (8 octets, 16 nibbles) + |