• mirc/identifiers/$decode
  Base32's decoder is designed to support Google Authenticator format, which means that it ign
  12 KB (1,991 words) - 09:37, 14 November 2022
• List of digital circuits
  * [[Encoder]]s / [[Decoder]]s
  615 bytes (65 words) - 16:22, 21 July 2014
• amd/am2900
  | {{\|AM2921}} || 1-to-8 [[decoder]] with 3-state outputs || 20 | {{\|AM2924}} || 3-to-8 [[decoder]]/[[demultiplexer]] || 16, 20
  9 KB (1,061 words) - 22:55, 18 June 2019
• intel/3000
  | {{\|3205}} || 1 of 8 binary decoder
  3 KB (308 words) - 05:03, 18 February 2020
• tesla (czech)/mh 3000
  | {{\|3205}} || 1 of 8 binary decoder
  2 KB (182 words) - 06:47, 22 January 2016
• 7400 series
  ...s chips such as [[and gates]] and [[or gates]] as well as [[register]]s, [[decoder]]s, and [[RAM]] units. | {{\|7447}} || BCD to 7-Segment Decoder/Driver; Open-Collector Outputs
  7 KB (851 words) - 20:53, 29 July 2021
• rockwell international/pps-4
  ...6}}, ROM ({{\|A05|A05xx}}), RAM ({{\|10432}}), and a [[7400 series]] 74154 decoder.
  3 KB (359 words) - 17:26, 19 May 2016
• atmel/marc4
  | {{\|M44C092}} || 4 kB || 256x4 b || 16 || SO20 || IR encoder & decoder | {{\|M44C092-H}} || 4 kB || 256x4 b || 16 || SO20 || IR encoder & decoder + phase control
  6 KB (787 words) - 21:05, 7 February 2016
• intel/mcs-80
  | {{\|8205}} || || 1 Of 8 Binary Decoder
  4 KB (406 words) - 16:10, 26 January 2019
• intel/microarchitectures/haswell (client)
  ...the complex 4-way decoder. The decoder has 3 simple decoders and 1 complex decoder. In total, they are capable of emitting 3 single fused µOps and an additio Continuing with the decoder is the [[register renaming]] stage. This is crucial for out-of-order execut
  27 KB (3,750 words) - 06:57, 18 November 2023
• intel/microarchitectures/sandy bridge (client)
  ...properties such as branches. As with previous microarchitectures, the pre-decoder has a [[throughput]] of 6 [[macro-ops]] per cycle or until all 16 bytes are ...other words, for each additional µOP the complex decoder emits, one less decoder is active.
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ...properties such as branches. As with previous microarchitectures, the pre-decoder has a [[throughput]] of 6 [[macro-ops]] per cycle or until all 16 bytes are ...other words, for each additional µOP the complex decoder emits, one less decoder is active.
  79 KB (11,922 words) - 06:46, 11 November 2022
• mathstar/arrix
  * [[:File:MPEG2 Multi-channel Decoder for FPOA.pdf|MPEG2 Multi-channel Decoder for FPOA]]
  4 KB (492 words) - 00:37, 28 June 2016
• amd/microarchitectures/zen
  ...an be emitted, usually only 4MOPs/cycle are emitted from the [[instruction decoder|decoders]].
  79 KB (12,095 words) - 15:27, 9 June 2023
• amd/microarchitectures/zen 2
  ...x86 instructions per cycle to macro-ops. According to AMD the instruction decoder can send up to four instructions per cycle to the op cache and micro-op que ...ructions. If they are fused when entering the cache, or if the instruction decoder sends fused macro-ops to the op cache as well as the micro-op queue is uncl
  57 KB (8,701 words) - 22:11, 9 October 2022
• mediatek/helio/mt6795
  * HEVC decoder 4k2k @ 30fps * H.264 decoder (30fps/40Mbps)
  5 KB (669 words) - 14:35, 5 August 2020
• mediatek/helio/mt6795m
  * HEVC decoder 4k2k @ 30fps * H.264 decoder (30fps/40Mbps)
  6 KB (647 words) - 09:57, 12 January 2018
• mediatek/helio/mt6795t
  * HEVC decoder 4k2k @ 30fps * H.264 decoder (30fps/40Mbps)
  6 KB (670 words) - 09:36, 22 August 2018
• mediatek/helio/mt6755
  * HEVC decoder 4k2k @ 30fps * H.264 decoder (30fps/40Mbps)
  5 KB (696 words) - 17:41, 15 August 2020
• mediatek/helio/mt6755m
  * HEVC decoder 4k2k @ 30fps * H.264 decoder (30fps/40Mbps)
  5 KB (614 words) - 09:40, 12 February 2020

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