• intel/mcs-4/4004
  ...|| rowspan="4" | Bidirectional data bus pins || rowspan="4" | Address and data communication to the ROM and RAM occurs on D0-D3. | 11 || CM-ROM || CM-ROM output || ROM selection signal used to retrieve data from memory.
  5 KB (748 words) - 21:37, 21 November 2021
• intel/core i7
  ...essors are [[quad-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0. All processors us * '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
  43 KB (5,739 words) - 21:30, 22 April 2024
• microprocessor
  ...circuits operating as a cohesive unit, designed for the processing digital data. ...oadest sense, their basic functionality is to continuously read in digital data consisting of instructions and possibly values; execute them by interpretin
  8 KB (1,149 words) - 00:41, 16 September 2019
• multiplexer
  A '''multiplexer''' ('''mux''') or a '''data selector''' or '''input selector''' is a [[combinational circuit]] device t ...single destination. Multiplexers are also heavily used in I/O operations, data buses, and register files. Additionally multiplexers have also found their
  10 KB (1,445 words) - 11:53, 18 November 2018
• read-only register
  ...gisters]], [[hardware timers]], [[counters]], and [[bus|data buses]] where data is only transmitted. Attempting to write to such registers typically result
  676 bytes (92 words) - 20:32, 31 July 2017
• amd/am2900
  ...division. The slices can be stacked to produce any multiple of 4-bit wide data path (8, 12, 16, 32, etc. bits) and memory address for use in larger system | {{\|AM2905}} || Quad 2-input bus transceiver || 24
  9 KB (1,061 words) - 22:55, 18 June 2019
• intel/3000
  | {{\|3216}} || Noninverting bidirectional bus driver | {{\|3226}} || Inverting bidirectional bus driver
  3 KB (308 words) - 05:03, 18 February 2020
• rockwell international/pps-4
  | {{\|10731}} || com data interface || | {{\|10738}} || Bus I/O ||
  3 KB (359 words) - 17:26, 19 May 2016
• intel/atom
  This table is generated automatically from the data in the actual articles. ...-header"><th>&nbsp;</th><th colspan="8">Main processor</th><th colspan="2">Bus</th><th colspan="3">Features</th></tr>
  17 KB (2,292 words) - 09:32, 16 July 2019
• amd/athlon
  ...ble data rate [[front side bus]] operating at 100 MHz (having an effective bus speed of 200 MHz). Argon microprocessors were manufactured in 250 nm proces ...ble data rate [[front side bus]] operating at 100 MHz (having an effective bus speed of 200 MHz). Pluto microprocessors were manufactured in 180 nm proces
  10 KB (1,163 words) - 10:41, 26 February 2019
• amd/am9080
  This table is generated automatically from the data in the actual articles. | {{\|Am8228}} || system controller & bus driver
  5 KB (683 words) - 23:46, 7 March 2018
• intel/mcs-8/isa
  | data size = 8 bit This ISA has an {{arch|8}} data and address bus. This architecture included seven 8-bit registers, 48 instructions, and int
  13 KB (2,079 words) - 09:11, 29 September 2019
• intel/microarchitectures/bonnell
  ...MT/s dual mode ([[gunning transceiver logic|GTL]] & [[CMOS]]) [[front side bus|FSB]] ** L1 Data Cache
  38 KB (5,468 words) - 20:29, 23 May 2019
• intel/microarchitectures/silvermont
  * {{x86|PREFETCHW|<code>PREFETCHW</code>}} - Prefetch data into caches, hinting a write is expected in the future ...by integrating and other support chips on-die, it still used a Front Side Bus implementation to talk to North Bridge. In Silvermont, this was replaced wi
  9 KB (1,160 words) - 09:35, 25 September 2019
• intel/pentium (2009)
  ...essors are [[dual-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0. These processors * '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
  20 KB (2,661 words) - 00:45, 11 October 2017
• intel/celeron
  ...essors are [[dual-core]] processors. These processors had the [[front-side bus|FSB]] replaced with {{intel|Direct Media Interface}} 1.0. These processors * '''Bus:''' {{intel|DMI}} (2.5 GT/s) interface
  25 KB (3,201 words) - 03:13, 22 September 2018
• intel/microarchitectures/sandy bridge (client)
  ** New SVID (Serial Voltage ID bus) ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ** Bus/Interface to Chipset ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB).
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/kaby lake
  ...sists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally there is a unified L2 TLB (STLB). ...} are a two-chip solution linked together via Intel's standard [[DMI 3.0]] bus interface which utilizes 4 of the CPU's 20 [[PCIe]] 3.0 lanes (having a tra
  38 KB (5,431 words) - 10:41, 8 April 2024
• intel/microarchitectures/ice lake (client)
  ** 1.4x higher data rates (3733 MT/s, up from 2666 MT/s) ...nit in the processor. All clock domains are some multiple of the [virtual] bus clock ([[BCLK]]).
  23 KB (3,613 words) - 12:31, 20 June 2021

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