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  • This is a '''[[has type::quantity]]''' property representing the size of the RAM of the microcontroller/IC.
    379 bytes (49 words) - 01:02, 19 May 2016
  • This is a '''[[has type::string]]''' property representing the size of the RAM in breakdown representation.
    152 bytes (23 words) - 03:20, 20 January 2016
  • {{title|Nanotube-RAM (NRAM)}} ...nge]] [[memory-class storage|memory-class storage]] [[random access memory|RAM]]. NRAM is proprietary technology developed by [[Nantero]] licenseable to m
    6 KB (1,010 words) - 02:42, 31 January 2019

Page text matches

  • === RAM information === # RAM Info #
    27 KB (3,608 words) - 11:41, 25 October 2018
  • ...e chip was capable of accessing 4KB of [[program memory]] and 640 bytes of RAM. The 4004 was part of the [[Intel MCS-4]] system. ...a bus pins || rowspan="4" | Address and data communication to the ROM and RAM occurs on D0-D3.
    5 KB (748 words) - 21:37, 21 November 2021
  • ! Number !! Launch Date !! GP I/O !! Timers !! RAM !! Flash (Inst/Prog) !! Cores !! Threads !! Clock !! TDP !! L2$ !! Package
    4 KB (434 words) - 03:31, 15 February 2016
  • ...'') - a microprocessor that contains a few additional components such as [[RAM]], [[ROM]], and programmable [[I/O]] ports primarily designed to control an
    8 KB (1,149 words) - 00:41, 16 September 2019
  • ** Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
    3 KB (314 words) - 23:04, 20 May 2018
  • * Minato, O., et al. "A Hi-CMOSII 8Kx8 bit static RAM." IEEE Journal of Solid-State Circuits 17.5 (1982): 793-798.
    8 KB (969 words) - 12:31, 22 February 2019
  • | ram = 8 B | ram break = 16x4 bit
    1 KB (119 words) - 14:45, 3 February 2016
  • ...plete system was made of 4 chips. The chipset included a [[ROM]] chip, a [[RAM]] chip, [[shift register]], and a [[4-bit architecture|4-bit]] [[microproce | {{hitachi|HD35402}} || RAM
    2 KB (266 words) - 00:54, 19 May 2016
  • ...ent set size''' ('''RSS''') is the amount of space of [[physical memory]] (RAM) held by a [[process]]. The value is typically specified in [[bytes]] or [[
    5 KB (692 words) - 10:20, 3 June 2020
  • ...nce Computer]] || [[discrete logic|discrete IC]] RTL || 2.048 MHz || 4 KB (RAM)<br />73.73 KB (ROM) || 70 lb
    11 KB (1,334 words) - 18:26, 10 May 2019
  • '''RAM:'''
    9 KB (1,150 words) - 00:03, 2 October 2022
  • * [[RAM]]s
    615 bytes (65 words) - 16:22, 21 July 2014
  • ! Part !! [[RAM]] !! [[ROM]] !! I/O Ports !! Notes
    2 KB (244 words) - 00:33, 19 May 2016
  • | ram = 120 b | ram break = 120x1 bits
    1 KB (140 words) - 05:28, 22 January 2016
  • ...oller supporting 16K and 64K [[mosfet|MOS]] dynamic [[random access memory|RAM]] || 40, 44 ...supporting 16K, 64K and 256K [[mosfet|MOS]] dynamic [[random access memory|RAM]] || 48, 68
    9 KB (1,061 words) - 22:55, 18 June 2019
  • ...28 Words (10-bit ea) of pattern ROM. 32 to 160 digits (4-bit ea) of data [[RAM]]. Chips also contained Event/Timer-Counter and 22-44 I/O lines. Output was ! Model !! ROM !! RAM !! Registers !! Stack Registers !! I/O Lines !! Part No.
    4 KB (400 words) - 19:05, 24 May 2016
  • | {{\|MN1400}} || 1024x8 ROM, 64x4 RAM || NMOS || General Purpose | {{\|MN1402}} || 7684x8 ROM, 32x4 RAM || NMOS ||
    4 KB (462 words) - 19:14, 13 October 2019
  • | {{matsushita|MN1542}} || 2048x8 ROM, 152x4 RAM, 28 I/O || NMOS || | {{matsushita|MN1544}} || 4096x8 ROM, 256x4 RAM, 28 I/O || NMOS ||
    3 KB (301 words) - 19:23, 13 October 2019
  • | {{\|10806}} || 32 words x 9-bit RAM
    2 KB (179 words) - 00:03, 3 February 2016
  • | {{\|MM57140}} || Single-chip; 630x8-bit ROM, 55x4-bit RAM | {{\|MM5785}} || [[RAM]] interface (between {{\|MM5782}} and {{\|MM5799}})
    2 KB (274 words) - 18:29, 5 February 2016

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