Semiconductor & Computer Engineering
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|tdp typical=20 W | |tdp typical=20 W | ||
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| − | '''Drive Xavier''' is a {{arch|64}} [[ARM]] high-performance autonomous machine [[ | + | '''Drive Xavier''' is a {{arch|64}} [[ARM]] high-performance autonomous machine [[neural processor]] designed by [[NVIDIA]] and introduced in [[2018]]. |
== Overview == | == Overview == | ||
| − | The Drive Xavier is an autonomous machine [[system on chip]] designed by [[NVIDIA]] and introduced at CES 2018. Silicon came back in the last week of December 2017 with sampling started in the first quarter of 2018. NVIDIA plans on mass production by the end of the year. NVIDIA reported that the product is a result of $2 billion R&D and 8,000 engineering hours. | + | The Drive Xavier is an autonomous machine [[system on chip]] designed by [[NVIDIA]] and introduced at CES 2018. Silicon came back in the last week of December 2017 with sampling started in the first quarter of 2018. NVIDIA plans on mass production by the end of the year. NVIDIA reported that the product is a result of $2 billion R&D and 8,000 engineering hours. The chip is said to have full redundancy and diversity in its functional blocks. That is, the SoC can continue to operate properly even after a fault is detected. |
| + | |||
| + | === Architecture === | ||
| + | ==== CPU ==== | ||
| + | {{main|nvidia/microarchitectures/carmel|l1=Carmel core}} | ||
| + | The chip features eight {{nvidia|Carmel|l=arch}} core, Nvidia's own custom {{arch|64}} [[ARM]] cores. Those cores have full ECC and parity as well as dual-execution (unknown if lockstep or something a bit different) allowing all code to execute twice for redundancy reasons. | ||
| + | ==== GPU ==== | ||
| + | {{main|nvidia/microarchitectures/volta|l1=Volta}} | ||
| + | The chip incorporates a {{nvidia|Volta|l=arch}} GPU with 512 {{nvidia|CUDA Cores}} capable of operating in 64-bit and 32-bit floating point as well as 8-bit integer. This allows the various [[deep learning]] [[artificial neural networks]] types to run efficiently in the format most suitable for them. This translates to 1.3 CUDA TOPS / 20 Tensor Core TOPS. | ||
| + | |||
| + | == Memory controller == | ||
| + | {{memory controller | ||
| + | |type=LPDDR4-2133 | ||
| + | |ecc=Yes | ||
| + | |width=32 bit | ||
| + | |channels=8 | ||
| + | |max bandwidth=127.1 GiB/s | ||
| + | }} | ||
== Die == | == Die == | ||
Revision as of 10:41, 10 January 2018
| Edit Values | |
| Drive Xavier | |
| General Info | |
| Designer | Nvidia |
| Manufacturer | TSMC |
| Market | Artificial Intelligence |
| Introduction | January 8, 2018 (announced) |
| General Specs | |
| Series | Drive |
| Microarchitecture | |
| ISA | ARMv8 (ARM) |
| Process | 12 nm |
| Transistors | 9,000,000,000 |
| Technology | CMOS |
| Die | 350 mm² |
| Word Size | 64 bit |
| Cores | 8 |
| Threads | 8 |
| Electrical | |
| TDP | 30 W |
| TDP (Typical) | 20 W |
Drive Xavier is a 64-bit ARM high-performance autonomous machine neural processor designed by NVIDIA and introduced in 2018.
Overview
The Drive Xavier is an autonomous machine system on chip designed by NVIDIA and introduced at CES 2018. Silicon came back in the last week of December 2017 with sampling started in the first quarter of 2018. NVIDIA plans on mass production by the end of the year. NVIDIA reported that the product is a result of $2 billion R&D and 8,000 engineering hours. The chip is said to have full redundancy and diversity in its functional blocks. That is, the SoC can continue to operate properly even after a fault is detected.
Architecture
CPU
- Main article: Carmel core
The chip features eight Carmel core, Nvidia's own custom 64-bit ARM cores. Those cores have full ECC and parity as well as dual-execution (unknown if lockstep or something a bit different) allowing all code to execute twice for redundancy reasons.
GPU
- Main article: Volta
The chip incorporates a Volta GPU with 512 CUDA Cores capable of operating in 64-bit and 32-bit floating point as well as 8-bit integer. This allows the various deep learning artificial neural networks types to run efficiently in the format most suitable for them. This translates to 1.3 CUDA TOPS / 20 Tensor Core TOPS.
Memory controller
 |
Integrated Memory Controller
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Die
| core count | 8 + |
| designer | Nvidia + |
| die area | 350 mm² (0.543 in², 3.5 cm², 350,000,000 µm²) + |
| first announced | January 8, 2018 + |
| full page name | nvidia/tegra/xavier + |
| has ecc memory support | true + |
| instance of | microprocessor + |
| isa | ARMv8 + |
| isa family | ARM + |
| ldate | 3000 + |
| manufacturer | TSMC + |
| market segment | Artificial Intelligence + |
| max memory bandwidth | 127.1 GiB/s (130,150.4 MiB/s, 136.473 GB/s, 136,472.586 MB/s, 0.124 TiB/s, 0.136 TB/s) + |
| max memory channels | 8 + |
| name | Drive Xavier + |
| process | 12 nm (0.012 μm, 1.2e-5 mm) + |
| series | Drive + |
| supported memory type | LPDDR4-2133 + |
| tdp | 30 W (30,000 mW, 0.0402 hp, 0.03 kW) + |
| tdp (typical) | 20 W (20,000 mW, 0.0268 hp, 0.02 kW) + |
| technology | CMOS + |
| thread count | 8 + |
| transistor count | 9,000,000,000 + |
| word size | 64 bit (8 octets, 16 nibbles) + |
