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=== Key changes from {{\\|Sunny Cove}}===
 
=== Key changes from {{\\|Sunny Cove}}===
 
* New cache subsystem
 
* New cache subsystem
 +
** 1.25MB L2 cache per core, up from 512KB per core in Sunny Cove
 
** 3MB L3 cache per core, 50% more than Sunny Cove
 
** 3MB L3 cache per core, 50% more than Sunny Cove
 
* Security features
 
* Security features

Revision as of 03:44, 21 November 2019

Edit Values
Willow Cove µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2020
Process10 nm
Instructions
ISAx86-64
Succession

Willow Cove is the successor to Sunny Cove, a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products, including Tiger Lake.

History

Intel Core roadmap

Willow Cove was originally unveiled by Intel at their 2018 architecture day. Willow Cove is intended to succeed Sunny Cove in the 2020 timeframe.

Process Technology

Willow Cove is designed to take advantage of Intel's 10 nm process.

Architecture

Key changes from Sunny Cove

  • New cache subsystem
    • 1.25MB L2 cache per core, up from 512KB per core in Sunny Cove
    • 3MB L3 cache per core, 50% more than Sunny Cove
  • Security features

This list is incomplete; you can help by expanding it.

New instructions

Willow Cove introduced a number of new instructions:

  • Control-flow Enforcement Technology (CET) enhancements
  • MOVDIR - Direct stores
  • Additional AVX-512 extensions:

Only on server parts (Sapphire Rapids):

Bibliography

  • Intel Architecture Day 2018, December 11, 2018
codenameWillow Cove +
designerIntel +
first launched2020 +
full page nameintel/microarchitectures/willow cove +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameWillow Cove +
process10 nm (0.01 μm, 1.0e-5 mm) +