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Difference between revisions of "compaq/microarchitectures/alpha 21464"
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|designer=Compaq | |designer=Compaq | ||
|manufacturer=IBM | |manufacturer=IBM | ||
| − | |||
|process=0.13 µm | |process=0.13 µm | ||
|cores=1 | |cores=1 | ||
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|l1d per=core | |l1d per=core | ||
|l1d desc=4-way set associative | |l1d desc=4-way set associative | ||
| + | |l2=3 MiB | ||
| + | |l2 per=core | ||
| + | |l2 desc=6-way set associative | ||
|predecessor=Alpha 21364 | |predecessor=Alpha 21364 | ||
|predecessor link=compaq/microarchitectures/alpha_21364 | |predecessor link=compaq/microarchitectures/alpha_21364 | ||
| Line 35: | Line 37: | ||
== Architecture == | == Architecture == | ||
{{empty section}} | {{empty section}} | ||
| + | |||
| + | == Area comparison == | ||
| + | In a talk by Joel Emer, it was stated that, at ISO process, the 21464 is roughly 4.5 times larger than the {{\\|21264}} and is over 6 times larger than the original {{\\|21064}}. | ||
== Die == | == Die == | ||
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: [[File:Alpha 21464 die floorplan.png|650px]] | : [[File:Alpha 21464 die floorplan.png|650px]] | ||
| + | == Documents == | ||
| + | * [[:File:alpha 21464.ppt|The Alpha 21364 and 21464 Microprocessors: Continuing the Performance Lead Beyond Y2K (PPT)]] ([[:File:alpha 21464.pdf|PDF Version]]) | ||
== References == | == References == | ||
* Seznec, André, et al. "Design tradeoffs for the Alpha EV8 conditional branch predictor." Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on. IEEE, 2002. | * Seznec, André, et al. "Design tradeoffs for the Alpha EV8 conditional branch predictor." Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on. IEEE, 2002. | ||
Latest revision as of 13:20, 31 March 2019
| Edit Values | |
| Alpha 21464 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Compaq |
| Manufacturer | IBM |
| Process | 0.13 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Stages | 8 |
| Decode | 8-way |
| Instructions | |
| ISA | Alpha |
| Cache | |
| L1I Cache | 64 KiB/core 4-way set associative |
| L1D Cache | 64 KiB/core 4-way set associative |
| L2 Cache | 3 MiB/core 6-way set associative |
| Succession | |
Alpha 21464 was an ambitious Alpha microarchitecture designed by Compaq as a successor to the Alpha 21364 set to be introduced in 2004. The project was cancelled in June 2001 when Compaq announced their commitment to Intel's Itanium.
Contents
History[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Process Technology[edit]
- See also: 0.13 µm process
| |
This section is empty; you can help add the missing info by editing this page. |
Architecture[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
Area comparison[edit]
In a talk by Joel Emer, it was stated that, at ISO process, the 21464 is roughly 4.5 times larger than the 21264 and is over 6 times larger than the original 21064.
Die[edit]
- 1.2 GHz - 2 GHz @ ~1.2 V
- 0.13 µm process
- ~250,000,000 transistors
- ~420 mm² die size
- PGA-??? package
- ~1100 signal pins
Floorplan was done but the design never made it to fabrication.
Documents[edit]
- The Alpha 21364 and 21464 Microprocessors: Continuing the Performance Lead Beyond Y2K (PPT) (PDF Version)
References[edit]
- Seznec, André, et al. "Design tradeoffs for the Alpha EV8 conditional branch predictor." Computer Architecture, 2002. Proceedings. 29th Annual International Symposium on. IEEE, 2002.
Facts about "Alpha 21464 - Microarchitectures - Compaq"
| codename | Alpha 21464 + |
| core count | 1 + |
| designer | Compaq + |
| full page name | compaq/microarchitectures/alpha 21464 + |
| instance of | microarchitecture + |
| instruction set architecture | Alpha + |
| manufacturer | IBM + |
| microarchitecture type | CPU + |
| name | Alpha 21464 + |
| pipeline stages | 8 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) + |
