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Alpha 21264 - Microarchitectures - DEC
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Alpha 21264 µarch
General Info
Arch TypeCPU
DesignerDEC
ManufacturerDEC, Intel, Samsung
IntroductionFebruary, 1998
Process0.35 µm
Core Configs1
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages6
Decode4-way
Instructions
ISAAlpha
Cache
L1I Cache64 KiB/core
2-way set associative
L1D Cache64 KiB/core
2-way set associative
Succession

Alpha 21264 was an Alpha microarchitecture designed by DEC and introduced in 1998 by Compaq as a successor to the Alpha 21164 architecture.

History[edit]

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Process Technology[edit]

See also: 0.35 µm process

Alpha 21264 was manufactured on a 0.35 µm process at DEC's own Hudson foundry. The process had a 0.35 µm drawn gate length and 0.25 µm effective channel length. The CMOS process had 3 metal layers. The chip allowed for a supply voltage of up to 2 V in order to limit the chips to a power limit of 72 W, although it was actually designed to reliably operate at up to 2.5 V.

Architecture[edit]

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  • Integrated PLL (designed by CSEM)

Die[edit]

  • 15,200,000 transistors
    • 9,200,000 cache
    • 6,000,000 logic
  • 0.35 µm 4 metal layers
  • 16.7 mm x 18.8 mm
  • 313.96 mm² die size
  • PGA-587 package
    • 389 signal pins


alpha 21264 die shot.png


alpha 21264 die shot (annotated).png

All Alpha 21264 chips[edit]

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References[edit]

  • Dobberpuhl, Daniel W. "Circuits and technology for Digital's StrongARM and ALPHA microprocessors [CMOS technology]." Advanced Research in VLSI, 1997. Proceedings., Seventeenth Conference on. IEEE, 1997.
codenameAlpha 21264 +
core count1 +
designerDEC +
first launchedFebruary 1998 +
full page namedec/microarchitectures/alpha 21264 +
instance ofmicroarchitecture +
instruction set architectureAlpha +
manufacturerDEC +, Intel + and Samsung +
microarchitecture typeCPU +
nameAlpha 21264 +
pipeline stages6 +
process350 nm (0.35 μm, 3.5e-4 mm) +