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Difference between revisions of "cavium/microarchitectures/vulcan"
< cavium

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(uarch details)
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{{cavium title|Vulcan|arch}}
 
{{cavium title|Vulcan|arch}}
−
{{microarchitecture}}
+
{{microarchitecture
 +
|atype=CPU
 +
|name=Vulcan
 +
|designer=Broadcomm
 +
|manufacturer=TSMC
 +
|introduction=2018
 +
|process=16 nm
 +
|cores=16
 +
|cores 2=20
 +
|cores 3=24
 +
|cores 4=28
 +
|cores 5=30
 +
|cores 6=32
 +
|type=Superscalar
 +
|type 2=Superpipeline
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages min=13
 +
|stages max=15
 +
|decode=4-way
 +
|isa=ARMv8.1
 +
|extension=NEON
 +
|l1i=32 KiB
 +
|l1i per=core
 +
|l1i desc=8-way set associative
 +
|l1d=32 KiB
 +
|l1d per=core
 +
|l1d desc=8-way set associative
 +
|l2=256 KiB
 +
|l2 per=core
 +
|l2 desc=8-way set associative
 +
|l3=1 MiB
 +
|l3 per=core
 +
}}
 
'''Vulcan''' is a high-performance {{arch|64}} [[ARM]] microarchitecture designed by [[Broadcom]] and later [[Cavium]] for the server market.
 
'''Vulcan''' is a high-performance {{arch|64}} [[ARM]] microarchitecture designed by [[Broadcom]] and later [[Cavium]] for the server market.
  
 
Introduced in [[2018]], Vulcan-based microprocessors are branded as part of the {{cavium|ThunderX2}} family.
 
Introduced in [[2018]], Vulcan-based microprocessors are branded as part of the {{cavium|ThunderX2}} family.

Revision as of 02:43, 27 May 2018

Edit Values
Vulcan µarch
General Info
Arch TypeCPU
DesignerBroadcomm
ManufacturerTSMC
Introduction2018
Process16 nm
Core Configs16, 20, 24, 28, 30, 32
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages13-15
Decode4-way
Instructions
ISAARMv8.1
ExtensionsNEON
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
8-way set associative
L3 Cache1 MiB/core

Vulcan is a high-performance 64-bit ARM microarchitecture designed by Broadcom and later Cavium for the server market.

Introduced in 2018, Vulcan-based microprocessors are branded as part of the ThunderX2 family.

Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/microarchitectures/vulcan&oldid=78822"
Facts about "Vulcan - Microarchitectures - Cavium"
RDF feed
codenameVulcan +
core count16 +, 20 +, 24 +, 28 +, 30 + and 32 +
designerBroadcomm +
first launched2018 +
full page namecavium/microarchitectures/vulcan +
instance ofmicroarchitecture +
instruction set architectureARMv8.1 +
manufacturerTSMC +
microarchitecture typeCPU +
nameVulcan +
pipeline stages (max)15 +
pipeline stages (min)13 +
process16 nm (0.016 μm, 1.6e-5 mm) +