Semiconductor & Computer Engineering
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Difference between revisions of "arm holdings/microarchitectures/cortex-a9"
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Revision as of 01:15, 31 December 2018
| Edit Values | |
| Cortex-A9 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | October 3, 2007 |
| Process | 40 nm |
| Succession | |
Cortex-A9 is the successor to the Cortex-A8, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
The Cortex-A9 was later succeeded by four independent lines - high-performance (A15), mainstream performance (A12), high efficiency (A7), and ultra-low power (A5).
Architecture
Key changes from Cortex-A8
- Fully synthesizable RTL (prior designs were hand/automated layout)
- 40 nm process (from 65 nm)
- New out-of-order pipeline (form in-order)
- Shorter pipeline (9-12 stages, down from 13)
- 2x frequency (2 GHz, up from 1 GHz)
- NEON
- Added Half precision support
This list is incomplete; you can help by expanding it.
Licensees
Arm named the following companies as licensees.
Facts about "Cortex-A9 - Microarchitectures - ARM"
| codename | Cortex-A9 + |
| designer | ARM Holdings + |
| first launched | October 3, 2007 + |
| full page name | arm holdings/microarchitectures/cortex-a9 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A9 + |
| process | 40 nm (0.04 μm, 4.0e-5 mm) + |
