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Difference between revisions of "arm holdings/microarchitectures/cortex-a9"
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The Cortex-A9 was later succeeded by four independent lines - high-performance ({{\\|Cortex-A15|A15}}), mainstream performance ({{\\|Cortex-A12|A12}}), high efficiency ({{\\|Cortex-A7|A7}}), and ultra-low power ({{\\|Cortex-A5|A5}}). | The Cortex-A9 was later succeeded by four independent lines - high-performance ({{\\|Cortex-A15|A15}}), mainstream performance ({{\\|Cortex-A12|A12}}), high efficiency ({{\\|Cortex-A7|A7}}), and ultra-low power ({{\\|Cortex-A5|A5}}). | ||
| + | |||
| + | == Architecture == | ||
| + | === Key changes from {{\\|Cortex-A8}} === | ||
| + | * Fully synthesizable RTL (prior designs were hand/automated layout) | ||
Revision as of 21:43, 29 December 2018
| Edit Values | |
| Cortex-A9 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | TSMC |
| Introduction | October 3, 2007 |
| Process | 40 nm |
| Succession | |
Cortex-A9 is the successor to the Cortex-A8, a low-power performance ARM microarchitecture designed by ARM Holdings for the mobile market. This microarchitecture is designed as a synthesizable IP core and is sold to other semiconductor companies to be implemented in their own chips.
The Cortex-A9 was later succeeded by four independent lines - high-performance (A15), mainstream performance (A12), high efficiency (A7), and ultra-low power (A5).
Architecture
Key changes from Cortex-A8
- Fully synthesizable RTL (prior designs were hand/automated layout)
Facts about "Cortex-A9 - Microarchitectures - ARM"
| codename | Cortex-A9 + |
| designer | ARM Holdings + |
| first launched | October 3, 2007 + |
| full page name | arm holdings/microarchitectures/cortex-a9 + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Cortex-A9 + |
| process | 40 nm (0.04 μm, 4.0e-5 mm) + |
