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Difference between revisions of "amd/packages/sp4r2"
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#REDIRECT [[amd/packages/sp4]]
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{{amd title|Package SP4r2}}
 +
{{package
 +
|name=SP4r2
 +
|designer=AMD
 +
|market=Embedded
 +
|first launched=February 21, 2018
 +
|microarch=Zen
 +
|tdp=55 W
 +
|package name=SP4r2
 +
|package type=FC-OBGA
 +
|package contacts=
 +
|package dimension=45 mm
 +
|package dimension 2=45 mm
 +
|package pitch=0.8 mm
 +
|contemporary=SP4
 +
|contemporary link=amd/packages/sp4
 +
}}
 +
'''SP4r2''' and its contemporary '''{{amd|SP4|l=pack}}''' are microprocessor packages of [[AMD]] {{amd|epyc embedded#3000 Series (Zen)|EPYC 3000}} "{{amd|Snowy Owl|l=core}}" embedded processors. Server processors of the same generation ({{amd|EPYC#7001 Series (Zen)|EPYC 7001}}) use {{\\|Socket SP3}}.
 +
 
 +
== Overview ==
 +
SP4 and SP4r2 are [[ball grid array]] packages with 0.8&nbsp;mm non-uniform pitch,<!--AMD-54945-3.00-NDA Sec 1.8.5 & 1.8.6--> 45&nbsp;mm × 45&nbsp;mm in size,<!--ibid.--> with [[flip chip]] die attachment and a stiffener frame. The processors using these packages are members of AMD's x86 CPU {{amd|CPUID#Family 23 (17h)|Family 17h}} with CPU cores based on the {{amd|Zen|l=arch}} microarchitecture, and are fabricated on a [[GlobalFoundries]] [[14 nm#GlobalFoundries|14&nbsp;nm]] process.
 +
 
 +
SP4r2 carries a "Zeppelin" ZP-B2<!--AMD-55449-1.19--> die. AMD used this die in various revisions for EPYC 7001 server and embedded processors, first generation Ryzen Threadripper {{abbr|HEDT}} and Ryzen desktop processors; see {{amd|CPUID#Family 23 (17h)|CPU Family 17h}}. The pin compatible<!--AMD-1887102-E--> {{amd|SP4|l=pack}} package uses two of these dies. It integrates eight CPU cores, two memory controllers, two 16-lane multi-function I/O interfaces and other I/O facilities. Both package types are intended for single processor systems so {{abbr|xGMI}} links are not supported. The multi-function I/O interfaces can be configured as PCIe, SATA, SATA Express,<!--AMD-54945--> or XGBE<!--ibid.--> links. The latter support the {{wp|10 Gigabit Ethernet#Backplane|10GBASE-KR}}, {{wp|Gigabit Ethernet#1000BASE-KX|1000BASE-KX}}, and {{wp|Media-independent interface#Serial gigabit media-independent interface|SGMII}} (10/100/1000 Mbit/s) backplane Ethernet protocols.
 +
 
 +
== Features ==
 +
* Lidless [[ball grid array]] package with stiffener frame, 45&nbsp;mm × 45&nbsp;mm
 +
** ? contacts, 0.8&nbsp;mm non-uniform pitch
 +
** Organic substrate, [[flip chip]] die attachment
 +
 
 +
* 2 × 72 bit DDR4 SDRAM interface
 +
** Up to 1333&nbsp;MHz, PC4-21333 (DDR4-2666), 42.67&nbsp;GB/s total raw bandwidth
 +
** Up to 2 DIMMs/channel
 +
** {{abbr|UDIMM}}, {{abbr|RDIMM}}, {{abbr|LRDIMM}}, {{abbr|NVDIMM-N}} types<!-- AMD-54945 -->
 +
** ECC support
 +
** Memory addressing up to ? GiB/channel
 +
** Max. total memory capacity 512 GiB using 4 × 128 GiB LRDIMMs
 +
 
 +
* Two multi-function I/O interfaces P0, G0
 +
:{| class="wikitable" style="text-align:center"
 +
|Lane||15||14||13||12||11||10||9||8||7||6||5||4||3||2||1||0
 +
|-
 +
|rowspan="5"|PCIe||colspan="16"|x16
 +
|-
 +
|colspan="8"|x8||colspan="8"|x8
 +
|-
 +
|colspan="4"|x4||colspan="4"|x4||colspan="4"|x4||colspan="4"|x4
 +
|-
 +
|colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2||colspan="2"|x2
 +
|-
 +
|x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1||x1
 +
|-
 +
|SATAe||colspan="12"| ||colspan="2"|1||colspan="2"|0
 +
|-
 +
|SATA||colspan="8"| ||7||6||5||4||3||2||1||0
 +
|-
 +
|XGBE||colspan="8"| ||3||2||1||0||colspan="4"|
 +
|-
 +
| ||colspan="4"|PHY 4||colspan="4"|PHY 3||colspan="4"|PHY 2||colspan="2"|PHY 1||colspan="2"|PHY 0
 +
|}
 +
:* PCIe Gen 1, 2, 3 (8&nbsp;GT/s) protocol supported on all interfaces
 +
:** 16 lanes, up to 8 ports per interface configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x4 + 4x1 + 1x8)
 +
:** Max. 7 PCIe ports in each 8-lane subset (e.g. 0x8 + 8x1 is not possible)
 +
:** Max. 7 PCIe ports per interface if any lane is configured as SATA port
 +
:** Different PCIe generations supported on the ports in the same interface
 +
:** Lane polarity inversion, per port lane reversal
 +
:** Up to 32 PCIe lanes total
 +
 
 +
:* SATA Express supported on the lowest four lanes of P0
 +
:** Combines PCIe and SATA controllers on the same two lanes with a {{abbr|GPIO}} pin for a device to indicate its controller type
 +
:** Up to 2 ports total
 +
 
 +
:* SATA Gen 1, 2, 3 (6&nbsp;Gb/s) protocol supported on the lower 8 lanes of P0
 +
 
 +
:* XGBE protocols supported on lanes 4-7 of P0
 +
 
 +
:* Five {{abbr|PHY}} groups on each interface
 +
:** Lanes sharing a PHY group must use the same protocol (PCIe, SATA, XGBE)
 +
 
 +
* 4 × USB 1.1, 2.0, 3.1 Gen 1 (5 Gb/s) ports
 +
 
 +
* Low speed interfaces: {{abbr|eMMC}}, {{abbr|UART}}, {{abbr|LPC}}, {{abbr|SPI/eSPI}}, {{abbr|I<sup>2</sup>C}}, {{abbr|SMBus}}, {{abbr|GPIO}}
 +
 
 +
== Processors using package SP4r2 ==
 +
<!-- NOTE:
 +
This table is generated automatically from the data in the actual articles.
 +
If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
created and tagged accordingly.
 +
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable">
 +
{{comp table header|cols|Cores|Threads|L2$|L3$|Base<br/>Frequ.|Turbo<br/>one core|Memory<br/>({{abbr|1DPC}})|Memory<br/>channels|T<sub>jmin</sub>|T<sub>jmax</sub>|{{abbr|cTDP}}↓|{{abbr|TDP}}|Launched|Price|{{abbr|LTB}}|{{abbr|OPN}}}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[package::SP4r2]]
 +
|?full page name
 +
|?model number
 +
|?core count
 +
|?thread count
 +
|?l2$ size
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency (1 core)#GHz
 +
|?supported memory type
 +
|?max memory channels
 +
|?min junction temperature#°C
 +
|?max junction temperature#°C
 +
|?tdp down
 +
|?tdp
 +
|?first launched
 +
|?release price
 +
|?last order
 +
|?part number
 +
|sort=model number
 +
|format=template
 +
|template=proc table 3
 +
|userparam=18
 +
|mainlabel=-
 +
|valuesep=,
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by amd]] [[package::SP4r2]]}}
 +
</table>
 +
{{comp table end}}
 +
 
 +
== Photos ==
 +
{{empty section}}
 +
 
 +
== Package Diagrams ==
 +
{| style="text-align: center;"
 +
|[[file:SP4 diag.svg]]<br/>SP4 package
 +
|&nbsp;
 +
|[[file:SP4r2 diag.svg]]<br/>SP4r2 package
 +
|}
 +
 
 +
== Pin Map ==
 +
{{empty section}}
 +
 
 +
== Bibliography ==
 +
* {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|file=3000-Family-Product-Brief.pdf|publ=AMD|pid=1887102|date=2018}}
 +
* {{cite techdoc|title=Product Brief: AMD EPYC™ Embedded 3000 Family|url=https://www.amd.com/system/files/documents/updated-3000-family-product-brief.pdf|publ=AMD|pid=1887102|rev=E|date=2019}}
 +
* {{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|url=https://developer.amd.com/wordpress/media/2017/11/54945_PPR_Family_17h_Models_00h-0Fh.pdf|publ=AMD|pid=54945|rev=1.14|date=2017-04-15}}
 +
* {{cite techdoc|title=Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors|publ=AMD|pid=54945|rev=3.00|date=2019-04-14}}
 +
* {{cite techdoc|title=Revision Guide for AMD Family 17h Models 00h-0Fh Processors|publ=AMD|pid=55449|rev=1.19|date=2019-12}}
 +
* [https://www.amd.com/en/products/specifications/embedded "Embedded Processor Specifications"]. AMD.com.
 +
 
 +
== See also ==
 +
* {{\\|SP4|Package SP4}}
 +
* {{\\|Socket SP3}}
 +
* {{\\|Socket TR4}}
 +
 
 +
[[Category:amd]]

Latest revision as of 05:09, 24 March 2023

Edit Values
SP4r2
General Info
DesignerAMD
IntroductionFebruary 21, 2018 (launched)
MarketEmbedded
MicroarchitectureZen
TDP55 W
55,000 mW
0.0738 hp
0.055 kW
Package
NameSP4r2
TypeFC-OBGA
Dimension45 mm
4.5 cm
1.772 in
× 45 mm
4.5 cm
1.772 in
Pitch0.8 mm
0.0315 in
Contemporary
SP4

SP4r2 and its contemporary SP4 are microprocessor packages of AMD EPYC 3000 "Snowy Owl" embedded processors. Server processors of the same generation (EPYC 7001) use Socket SP3.

Overview[edit]

SP4 and SP4r2 are ball grid array packages with 0.8 mm non-uniform pitch, 45 mm × 45 mm in size, with flip chip die attachment and a stiffener frame. The processors using these packages are members of AMD's x86 CPU Family 17h with CPU cores based on the Zen microarchitecture, and are fabricated on a GlobalFoundries 14 nm process.

SP4r2 carries a "Zeppelin" ZP-B2 die. AMD used this die in various revisions for EPYC 7001 server and embedded processors, first generation Ryzen Threadripper HEDT and Ryzen desktop processors; see CPU Family 17h. The pin compatible SP4 package uses two of these dies. It integrates eight CPU cores, two memory controllers, two 16-lane multi-function I/O interfaces and other I/O facilities. Both package types are intended for single processor systems so xGMI links are not supported. The multi-function I/O interfaces can be configured as PCIe, SATA, SATA Express, or XGBE links. The latter support the 10GBASE-KR, 1000BASE-KX, and SGMII (10/100/1000 Mbit/s) backplane Ethernet protocols.

Features[edit]

  • Lidless ball grid array package with stiffener frame, 45 mm × 45 mm
    •  ? contacts, 0.8 mm non-uniform pitch
    • Organic substrate, flip chip die attachment
  • 2 × 72 bit DDR4 SDRAM interface
    • Up to 1333 MHz, PC4-21333 (DDR4-2666), 42.67 GB/s total raw bandwidth
    • Up to 2 DIMMs/channel
    • UDIMM, RDIMM, LRDIMM, NVDIMM-N types
    • ECC support
    • Memory addressing up to ? GiB/channel
    • Max. total memory capacity 512 GiB using 4 × 128 GiB LRDIMMs
  • Two multi-function I/O interfaces P0, G0
Lane 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIe x16
x8 x8
x4 x4 x4 x4
x2 x2 x2 x2 x2 x2 x2 x2
x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1
SATAe 1 0
SATA 7 6 5 4 3 2 1 0
XGBE 3 2 1 0
PHY 4 PHY 3 PHY 2 PHY 1 PHY 0
  • PCIe Gen 1, 2, 3 (8 GT/s) protocol supported on all interfaces
    • 16 lanes, up to 8 ports per interface configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x4 + 4x1 + 1x8)
    • Max. 7 PCIe ports in each 8-lane subset (e.g. 0x8 + 8x1 is not possible)
    • Max. 7 PCIe ports per interface if any lane is configured as SATA port
    • Different PCIe generations supported on the ports in the same interface
    • Lane polarity inversion, per port lane reversal
    • Up to 32 PCIe lanes total
  • SATA Express supported on the lowest four lanes of P0
    • Combines PCIe and SATA controllers on the same two lanes with a GPIO pin for a device to indicate its controller type
    • Up to 2 ports total
  • SATA Gen 1, 2, 3 (6 Gb/s) protocol supported on the lower 8 lanes of P0
  • XGBE protocols supported on lanes 4-7 of P0
  • Five PHY groups on each interface
    • Lanes sharing a PHY group must use the same protocol (PCIe, SATA, XGBE)
  • 4 × USB 1.1, 2.0, 3.1 Gen 1 (5 Gb/s) ports

Processors using package SP4r2[edit]

ModelCoresThreadsL2$L3$Base
Frequ.		Turbo
one core		Memory
(1DPC)		Memory
channels		TjminTjmaxcTDP↓TDPLaunchedPriceLTBOPN
3101442 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
2.1 GHz
2,100 MHz
2,100,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
DDR4-266620 °C
273.15 K
32 °F
491.67 °R
95 °C
368.15 K
203 °F
662.67 °R
35 W
35,000 mW
0.0469 hp
0.035 kW
21 February 20182028PE3101BIR4KAF
3151482 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
2.7 GHz
2,700 MHz
2,700,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
DDR4-266620 °C
273.15 K
32 °F
491.67 °R
95 °C
368.15 K
203 °F
662.67 °R
45 W
45,000 mW
0.0603 hp
0.045 kW
21 February 20182028PE3151BJR48AF
3201884 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
1.5 GHz
1,500 MHz
1,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-213320 °C
273.15 K
32 °F
491.67 °R
95 °C
368.15 K
203 °F
662.67 °R
30 W
30,000 mW
0.0402 hp
0.03 kW
21 February 20182028PE3201BHR88AF
32518164 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-266620 °C
273.15 K
32 °F
491.67 °R
105 °C
378.15 K
221 °F
680.67 °R
55 W
55,000 mW
0.0738 hp
0.055 kW
21 February 2018$ 315.00
€ 283.50
£ 255.15
¥ 32,548.95
2028PE3251BGR88AF
32558164 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-26662-40 °C
233.15 K
-40 °F
419.67 °R
105 °C
378.15 K
221 °F
680.67 °R
30 W
30,000 mW
0.0402 hp
0.03 kW
55 W
55,000 mW
0.0738 hp
0.055 kW
2028PE3255BGR88AF
Count: 5

Photos[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Package Diagrams[edit]

SP4 diag.svg
SP4 package 		  SP4r2 diag.svg
SP4r2 package

Pin Map[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Bibliography[edit]

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/packages/sp4r2&oldid=101377"
Facts about "Package SP4r2 - AMD"
RDF feed
designerAMD +
first launchedFebruary 21, 2018 +
instance ofpackage +
market segmentEmbedded +
microarchitectureZen +
nameSP4r2 +
packageSP4r2 +
package length45 mm (4.5 cm, 1.772 in) +
package pitch0.8 mm (0.0315 in) +
package typeFC-OBGA +
package width45 mm (4.5 cm, 1.772 in) +
tdp55 W (55,000 mW, 0.0738 hp, 0.055 kW) +