Semiconductor & Computer Engineering
From WikiChip
Search results
- | microarch 6 = Broadwell | proc = 45 nm43 KB (5,739 words) - 21:30, 22 April 2024
- | microarch 6 = Westmere | proc = 350 nm13 KB (1,417 words) - 12:37, 22 December 2018
- |process=5 nm |process 2=6 nm4 KB (693 words) - 01:48, 2 April 2023
- |process=5 nm |process 2=6 nm4 KB (666 words) - 01:48, 2 April 2023
- [[File:intel mask.jpg|right|thumb|Modern Intel 6" [[14 nm]]/[[10 nm]] test reticle.]]3 KB (533 words) - 17:17, 29 January 2024
- | process = 22 nm |l3 cache=6 MiB4 KB (404 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (401 words) - 14:24, 12 February 2019
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (400 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:22, 13 December 2017
- |process=22 nm |l3 cache=6 MiB3 KB (386 words) - 09:14, 26 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (401 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (397 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (398 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB4 KB (406 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (396 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (391 words) - 16:22, 13 December 2017
- | process = 22 nm |l3 cache=6 MiB3 KB (399 words) - 16:27, 13 December 2017
- |core family=6 |process=14 nm4 KB (596 words) - 16:15, 13 December 2017
- |core family=6 |process=14 nm4 KB (596 words) - 16:15, 13 December 2017
- |core family=6 |process=14 nm4 KB (627 words) - 16:17, 13 December 2017
- |core family=6 |process=14 nm4 KB (627 words) - 16:20, 13 December 2017
- |core family=6 |process=14 nm4 KB (640 words) - 02:21, 16 January 2019
- |core family=6 |process=14 nm4 KB (650 words) - 02:21, 16 January 2019
- | process = 14 nm |l3 cache=6 MiB4 KB (407 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (401 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (395 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (424 words) - 16:22, 13 December 2017
- | process = 14 nm |l3 cache=6 MiB4 KB (405 words) - 16:22, 13 December 2017
- |process=14 nm |l3 cache=6 MiB4 KB (460 words) - 15:03, 24 March 2019
- |core family=6 |process=14 nm4 KB (631 words) - 16:18, 13 December 2017
- |core family=6 |process=14 nm4 KB (649 words) - 16:20, 13 December 2017
- | proc = 45 nm | proc 2 = 32 nm17 KB (2,292 words) - 09:32, 16 July 2019
- | proc = 800 nm | proc 2 = 600 nm10 KB (1,057 words) - 19:30, 1 November 2021
- | microarch 6 = Excavator | proc = 32 nm6 KB (700 words) - 15:43, 1 December 2019
- ...lithography process|28 nm process]] (HN) / [[22 nm lithography process|22 nm process]] (FN) in 2012. TSMC cancelled its planned 32nm node process. Intel's 32 nm process became the first process to introduce the [[self-aligned via patter10 KB (1,090 words) - 19:14, 8 July 2021
- ...e 14 nm node was introduced in 2014/2015 and has been replaced by the [[10 nm process]]. | process 1 lith = 193 nm17 KB (2,243 words) - 19:32, 25 May 2023
- | process = 14 nm |l1d desc=6-way set associative4 KB (462 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative4 KB (472 words) - 16:15, 13 December 2017
- |process=14 nm |l1d desc=6-way set associative4 KB (475 words) - 17:42, 27 March 2018
- | process = 14 nm |l1d desc=6-way set associative5 KB (573 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative5 KB (572 words) - 16:15, 13 December 2017
- | process = 14 nm |l1d desc=6-way set associative6 KB (744 words) - 18:35, 14 January 2019
- |process=14 nm |l1d desc=6-way set associative5 KB (736 words) - 03:44, 19 August 2023
- | process = 14 nm |l1d desc=6-way set associative5 KB (558 words) - 16:15, 13 December 2017
- ...lithography process|40 nm process]] (HN) / [[32 nm lithography process|32 nm process]] (FN) in 2010. ...on, {{intel|Fab 32}} in Arizona and {{intel|Fab 28}} in Israel. Intel's 45 nm process is the first time high-k + metal gate transistors was used in high-5 KB (602 words) - 05:51, 20 July 2018
- |process=45 nm |extension 6=SSSE338 KB (5,468 words) - 20:29, 23 May 2019
- | process = 32 nm | extension 6 = SSSE37 KB (872 words) - 19:42, 30 November 2017
- | process = 22 nm | extension 6 = SSSE39 KB (1,160 words) - 09:35, 25 September 2019
- | process = 14 nm | extension 6 = SSSE35 KB (568 words) - 19:40, 30 November 2017
