• mirc/string manipulation
  ...ing manipulation''' is the building block of many of today's utilities and algorithms. Everything from formatting and validation to analysis and manipulation req
  9 KB (1,360 words) - 13:07, 11 February 2019
• mirc/hash tables
  ...or to v7.52. It changed again for v7.53, and there were probably different algorithms at other times in the past.
  30 KB (5,149 words) - 01:46, 30 November 2018
• c/complex.h
  The {{C|algorithms|pragmas}}:
  13 KB (1,987 words) - 20:46, 7 January 2015
• programming language
  ...rmalization of programming languages through mathematical abstractions and algorithms due to concepts such as [[Wikipedia:Alonzo Church|Alonzo Church's]] [[lambd
  2 KB (220 words) - 01:42, 10 July 2016
• schlemiel the painter's algorithm
  [[category:algorithms]]
  4 KB (646 words) - 00:56, 21 February 2016
• secure hash standard
  ...[National Institute of Standards and Technology|NIST]] that specifies hash algorithms that can be used to generate digests of messages. ...PS PUB 180-4''' which was published in Aug 2015 and includes the following algorithms: SHA-1, SHA-224, SHA-256, SHA-384, SHA-512, SHA-512/224 and SHA-512/256.
  525 bytes (76 words) - 19:16, 25 November 2015
• intel/microarchitectures/sandy bridge (client)
  ...nce and throughput as well as speedup the throughput of various encryption algorithms. Sandy Bridge incorporates either two or four [[physical cores]] with eithe ...CU extends on this functionality with numerous state machines and firmware algorithms. The use of firmware, which Intel Fellow Opher Kahn described at IDF 2010,
  84 KB (13,075 words) - 00:54, 29 December 2020
• intel/microarchitectures/skylake (client)
  ...64 µOPs per thread. The LSD is particularly excellent in for many common algorithms that are found in many programs (e.g., tight loops, intensive calc loops, s ...platform power provided to the chip. The chip uses a number of autonomous algorithms (one for "Low Range" and one for "High Range"). The Low Range algorithm fre
  79 KB (11,922 words) - 06:46, 11 November 2022
• intel/microarchitectures/ice lake (client)
  ** {{x86|AVX512BITALG|<code>AVX512BITALG</code>}} - AVX-512 Bit Algorithms
  23 KB (3,613 words) - 12:31, 20 June 2021
• intel/80486
  ...external communication delays altogether. Furthermore more aggressive math algorithms were used to implement the new [[FPU]] yielding faster floating point calcu
  8 KB (953 words) - 08:27, 29 October 2022
• ambric/am2000
  ...ions that may benefit from [[instruction-level parallelism]] and iterative algorithms. The datapath itself is a self-synchronizing Ambric Channel with 3-stages.
  11 KB (1,421 words) - 14:45, 9 December 2018
• amd/microarchitectures/zen 2
  ...er hardware implementations compared to some of the other machine learning algorithms. They also tend to be more accurate than predictors like gshare but they do
  57 KB (8,701 words) - 22:11, 9 October 2022
• many-core microprocessor
  ...aspects such as power or throughput (i.e. optimized for specific types of algorithms or tasks) at the expense of other characteristics (e.g. serial code perform
  1 KB (208 words) - 22:39, 1 August 2021
• cavium/microarchitectures/cnmips
  ** ZIP engine supporting fixed or dynamic [[Huffman code]] compression algorithms, [[GZIP]], [[PKZIP]]
  7 KB (870 words) - 19:38, 23 June 2017
• cavium/octeon
  ...r compression/decompression algorithms (e.g.[[GZIP]]), and security/crypto algorithms (e.g. [[DES]], [[AES]], [[MD5]], and [[SHA1]]).
  11 KB (1,489 words) - 09:25, 30 December 2020
• x86/avx-512
  ; '''AVX512_BITALG''' - {{x86|AVX512_BITALG|'''AVX-512 Bit Algorithms'''}}
  83 KB (13,667 words) - 15:45, 16 March 2023
• apple/ax/a11
  ...ent. Based on those properties the encoder can optimize the video encoding algorithms for quality and compression level. ...rates a new [[neural engine]] which implements a set of [[machine learning algorithms]] designed to accelerate image recognition. The engine, a dual-core design,
  4 KB (661 words) - 23:51, 3 January 2021
• voltage regulator module
  ...on to being much more expensive, they also require fairly complex code and algorithms to be implemented in order to be effective. It's also worth pointing out th
  18 KB (3,026 words) - 16:55, 19 January 2020
• neural processor
  ...ary control and arithmetic logic necessary to execute [[machine learning]] algorithms, typically by operating on [[predictive models]] such as [[artificial neura ...and arithmetic logic components necessary to execute [[machine learning]] algorithms. NPUs are designed to accelerate the performance of common machine learning
  5 KB (640 words) - 16:27, 26 September 2023
• Power ISA v3.0
  <h3>Support Emerging Algorithms</h3>
  1 KB (164 words) - 08:38, 8 November 2017
• hardware acceleration
  ...the performance of certain algorithms continues. Additionally, repetitive algorithms can consume a large amount of the processor's resources. Hardware accelerat
  1 KB (171 words) - 20:29, 19 November 2017
• accelerator
  ...performing the equivalent of software code executing computationally heavy algorithms, the result is almost always either higher performance or higher power effi ...ion accelerator]]''' - accelerators that perform compression using various algorithms
  4 KB (539 words) - 19:47, 2 April 2019
• intel/innovation engine
  | Crypto Algorithms || {{tchk|yes}} || {{tchk|yes}}
  2 KB (324 words) - 04:46, 1 January 2018
• nvidia/tegra/xavier
  ...bility and perhaps offer a way to implement some of the more common set of algorithms slightly more efficiently. ...capable of implementing some of the common filter loop and other detection algorithms (e.g. [[Harris corner]], [[fast Fourier transform|FFTs]]). For each of the
  8 KB (1,263 words) - 03:08, 9 December 2019
• zhaoxin/microarchitectures/zhangjiang
  ** Support for Chinese Hash Algorithms [[SM3]] and [[SM4]]
  1 KB (178 words) - 21:12, 15 September 2021
• greenwaves/gap8
  ...or DPS-centric operations, specifically operations frequently found in the algorithms executed by the compute engine. Specific instructions were added for operat
  6 KB (981 words) - 14:11, 28 February 2018
• interconnect architecture
  ...rganization, physical [[floorplan]], arbitration blocks, protocol, routing algorithms, clocking, and power.
  372 bytes (45 words) - 13:01, 9 March 2018
• intel/cores/cascade lake sp
  ...tel|DL Boost}}, an {{x86|extension}} designed to speed up machine learning algorithms. Those processors support between two and eight-way multi-processing (the e
  9 KB (1,291 words) - 13:48, 27 February 2020
• intel/microarchitectures/polaris
  Intel implemented key numerical algorithms from LAPACK on Polaris. Polaris, 110 °C, can achieve a [[maximum frequency
  16 KB (2,552 words) - 23:22, 17 May 2019
• amd/microarchitectures/zen 4
  ** {{x86|AVX512_BITALG}} - Bit Algorithms (Ice Lake)
  13 KB (1,821 words) - 19:28, 13 November 2023
• arm/armv8
  ...ccelerators]]. Geared for small instruction-level crypto support, two main algorithms were supported: [[AES]] and [[SHA]] (SHA-1 and SHA-256).
  6 KB (817 words) - 06:37, 24 April 2020
• x86/avx512 vnni
  ...AVX-512}}, designed to accelerate [[convolutional neural network]]-based [[algorithms]].
  6 KB (1,048 words) - 16:52, 15 March 2023
• brain floating-point format
  ...oat16 is designed to be used in hardware [[accelerating]] machine learning algorithms. Bfloat was first proposed and implemented by [[Google]] with [[Intel]] sup
  4 KB (582 words) - 12:35, 26 April 2021
• memory scrubbing
  ...i-bit error problem which cannot be corrected by the various multi-bit ECC algorithms. Scrubbing takes advantage of the low probability of having two strikes in
  2 KB (278 words) - 02:08, 26 November 2018
• intel/microarchitectures/sunny cove
  ** {{x86|AVX512BITALG|<code>AVX512BITALG</code>}} - AVX-512 Bit Algorithms ...70 µOPs per thread. The LSD is particularly excellent in for many common algorithms that are found in many programs (e.g., tight loops, intensive calc loops, s
  34 KB (5,187 words) - 06:27, 17 February 2023
• intel/programmable unified memory architecture
  ...esigned by Intel specifically for the acceleration of graph data and graph algorithms. This is a new architecture designed for small irregular memory accesses ac
  2 KB (293 words) - 22:16, 4 August 2019
• microsoft/msfp8
  ...ed for the very same purpose of hardware [[accelerating]] machine learning algorithms. MSFP was first proposed and implemented by [[Microsoft]].
  1 KB (190 words) - 16:41, 15 October 2019
• x86/avx512 bf16
  ...on, part of {{x86|AVX-512}}, designed to accelerate neural network-based [[algorithms]] by performing dot-product on [[bfloat16]].
  4 KB (578 words) - 16:50, 15 March 2023
• arm holdings/microarchitectures/cortex-a510
  ...the Cortex-A510 design. There are multiple complementary data prefetching algorithms implemented on the Cortex-A510.
  15 KB (2,282 words) - 11:20, 10 January 2023
• alchemy/au1550-333mbc
  ** DES, 3DES, AES, ARC4 encryption algorithms ** MD5, SHA1 hash algorithms
  4 KB (613 words) - 09:17, 17 March 2022
• alchemy/au1550-333mbd
  ** DES, 3DES, AES, ARC4 encryption algorithms ** MD5, SHA1 hash algorithms
  4 KB (616 words) - 09:23, 17 March 2022
• alchemy/au1550-333mbf
  ** DES, 3DES, AES, ARC4 encryption algorithms ** MD5, SHA1 hash algorithms
  4 KB (623 words) - 09:25, 17 March 2022
• alchemy/au1550-333mbi
  ** DES, 3DES, AES, ARC4 encryption algorithms ** MD5, SHA1 hash algorithms
  4 KB (624 words) - 09:28, 17 March 2022
• alchemy/au1550-400mbc
  ** DES, 3DES, AES, ARC4 encryption algorithms ** MD5, SHA1 hash algorithms
  4 KB (604 words) - 09:30, 17 March 2022
• alchemy/au1550-400mbd
  ** DES, 3DES, AES, ARC4 encryption algorithms ** MD5, SHA1 hash algorithms
  4 KB (603 words) - 09:32, 17 March 2022
• alchemy/au1550-500mbc
  ** DES, 3DES, AES, ARC4 encryption algorithms ** MD5, SHA1 hash algorithms
  4 KB (604 words) - 09:33, 17 March 2022
• alchemy/au1550-500mbd
  ** DES, 3DES, AES, ARC4 encryption algorithms ** MD5, SHA1 hash algorithms
  4 KB (603 words) - 09:38, 17 March 2022
• alchemy/alchemy
  * DES, 3DES, AES, ARC4 encryption algorithms * MD5, SHA1 hash algorithms
  31 KB (4,972 words) - 03:09, 20 March 2022
• x86/avx512 bitalg
  {{x86 title|AVX-512 Bit Algorithms (BITALG)}}{{x86 isa main}} '''AVX-512 Bit Algorithms''' ('''AVX512_BITALG''') is an [[x86]] extension and part of the {{x86|AVX-
  5 KB (866 words) - 01:53, 14 March 2023
• x86/avx512 4vnniw
  ...i many-core products) to accelerate [[convolutional neural network]]-based algorithms. It was not implemented on other chips but partially revived with {{x86|AVX
  3 KB (475 words) - 15:28, 15 March 2023

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