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- |cache=Yes should probably added at one point:38 KB (5,468 words) - 20:29, 23 May 2019
- | cache = Yes * {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction9 KB (1,160 words) - 09:35, 25 September 2019
- |cache=Yes ...part identical to {{\\|Haswell}} with several enhancements, including new instruction set extensions.14 KB (1,891 words) - 14:37, 6 January 2022
- |cache=Yes * Cache27 KB (3,750 words) - 06:57, 18 November 2023
- | {{intel|Sandy Bridge E|l=core}} || SNB-E || Workstations & entry-level servers ...="2" | {{intel|Celeron}} || style="text-align: left;" rowspan="2" | Entry-level Budget || [[1 cores|1]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {84 KB (13,075 words) - 00:54, 29 December 2020
- |side cache=128 MiB |side cache per=package79 KB (11,922 words) - 06:46, 11 November 2022
- |side cache=64 MiB |side cache per=package38 KB (5,431 words) - 10:41, 8 April 2024
- ...=core}} || CFL-E || Mehlow || Workstation || GT2 || Workstations and entry-level servers ...(2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || 4xxx || Entry-level Budget || [[dual-core|Dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} |30 KB (4,192 words) - 13:48, 10 December 2023
- ** 2-level predictor with 8192 entry branch history table *** Does not store target addresses. Target addresses are calculated during instruction decode4 KB (578 words) - 18:57, 22 May 2019
- | [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk | desc 5 = '''Performance Level'''<br><table><tr><td style="width: 50px;">'''9'''</td><td>Extreme (Ryzen Th79 KB (12,095 words) - 15:27, 9 June 2023
- | [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tch Zen 2 inherits most of the design from {{\\|Zen+}} but improves the instruction stream bandwidth and floating-point throughput performance.57 KB (8,701 words) - 22:11, 9 October 2022
- ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.29 KB (3,752 words) - 13:14, 19 April 2023
- ...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.33 KB (4,255 words) - 17:41, 1 November 2018
- ** Instruction grouping at dispatch has been removed * Cache14 KB (1,905 words) - 23:38, 22 May 2020
- |cache=Yes * Large scale cache coherency7 KB (940 words) - 00:12, 8 March 2021
- ...ementation]]. In particular, the "Alpha" refers to [[DEC]]'s [[Alpha AXP]] instruction set architecture while the "21064" refers to a "21st century"-ready {{arch| ...r CMOS-3 process ([[1 µm]]). For that reason those chips also had reduced cache amount, in addition to no FPU support.4 KB (527 words) - 02:09, 4 August 2017
- ...).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || [[6 cores|6]] - [[8 cores|8]] || {{tchk ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)52 KB (7,651 words) - 00:59, 6 July 2022
- * Cache ** Improved cache prefetch11 KB (1,613 words) - 08:39, 3 March 2024
- ...The PEs do not maintain [[cache-coherency]] and there is no per-PE [[data cache]]. Complex instructions are processed by the Special Function Units (SFU) l ...2 KiB of [[level 1 data cache]]. Each '''City''' is made of 64 KiB of [[L2 cache]], a number of special function units, and 4 smaller blocks called "Village6 KB (838 words) - 09:33, 9 May 2019
- ...).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tc ** New {{x86|CPUID}} Level Type field for "die"32 KB (4,535 words) - 05:44, 9 October 2022
- ** 4-way instruction decode * Cache13 KB (1,962 words) - 14:48, 21 February 2019
- *** Larger [[instruction queue]] (40 entries, up from 24) *** Larger [[instruction fetch]] (48B/cycle, up from 24B/cycle)20 KB (3,149 words) - 10:44, 15 February 2020
- ...ssary. This core has its own 16 KiB of data cache and 4 KiB of instruction cache. ...programmed using the familiar standard GCC/GDB toolchain derived from the one developed by the RISC-V foundation. Currently two real-time operating syste6 KB (981 words) - 14:11, 28 February 2018
- ...words can be transferred each cycle between the register file and the data cache. Additionally, up to four 32-bit data words can be issued to the two FMA un ...54]] [[single-precision]] operands and is designed to sustain a single FMA instruction every 250ps (4 GHz). The multiplier itself is a [[Wallace tree]] of 4-2 car16 KB (2,552 words) - 23:22, 17 May 2019
- *** Half L2 Cache Size (256 KiB, down form 512 KiB) * Cache17 KB (2,449 words) - 22:11, 4 October 2019
- ** Larger [[instruction queue]] (48 entries, up from 40) * Cache5 KB (680 words) - 14:43, 16 March 2023
- ** 25% more [[last level cache]] (up to 20 MiB, up from 16 MiB) * Cache10 KB (1,357 words) - 18:48, 13 September 2022
- Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on N ...4c [referred to as “Zen 4D” in leaks] core sacrificing half of the L3 cache.)13 KB (1,821 words) - 19:28, 13 November 2023
- The Neoverse N1 has a private L1I, L1D, and L2 cache. * Cache7 KB (980 words) - 13:46, 18 February 2023
- *** Decoupled from the instruction fetch The Cortex-A76 has a private L1I, L1D, and L2 cache.14 KB (2,183 words) - 17:15, 17 October 2020
- ** New [[L0]] MOP cache ** 1.5x wider instruction fetch (6 instrs/cycle, up from 4)17 KB (2,555 words) - 06:08, 16 June 2023
- ** Additional instruction fusion cases **** New packaging scheme (improve instruction density)21 KB (3,067 words) - 09:25, 31 March 2022
- ...ced in [[2011]] which brought a large number of fundamental changes to the instruction set, including the introduction of 64-bit operating capabilities. ...what was previously {{\\|ARMv7}}. It covers the {{\\|A32}} and {{\\|T32}} instruction sets along with a number of new instructions. AArch32 keeps the classical A6 KB (817 words) - 06:37, 24 April 2020
- ...s full languages such as C++ and executes full programs. There is a one-to-one correspondence between the nodes in the compiler-generated graph and the CS ...are configured. The CSA can be partitioned into [[privileged]] and [[user-level]] state. This can allow a primary configuration of the fabric to run withou14 KB (2,130 words) - 20:19, 2 October 2018
- ...er 26 2017 with a complete lineup that ranges from a workstation featuring one vector engine (VE) card to a full supercomputer with 64 VEs. NEC disclosed *** L1I Cache:16 KB (2,497 words) - 13:30, 15 May 2020
- ** 1.5x larger µOP cache (2.3K entries, up from 1536) ** Data Cache34 KB (5,187 words) - 06:27, 17 February 2023
- One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. ** Level 1 instruction cache switched to [[PIPT]] (from [[VIPT]])3 KB (347 words) - 14:40, 31 December 2018
- "As one of the leading vendors of embedded ARM7TDMI applications, with extensive ex ...ction regions. These can be specified as to base address, region size, and cache/buffer properties. During debug, the ARM940T provides full debug access to8 KB (1,261 words) - 22:05, 29 December 2018
- ** Larger [[instruction queue]] (60 entries, up from 48) * Cache3 KB (333 words) - 22:10, 27 July 2021
- * Cache ** L1I Cache7 KB (947 words) - 10:20, 9 September 2022
- * Cache ** L1I Cache:24 KB (3,792 words) - 04:37, 30 September 2022
- ...ssets/content_type/white_papers_and_tech_docs/21086.pdf SYSCALL and SYSRET Instruction Specification Application Note]||1998-05-01|| ...https://www.amd.com/system/files/TechDocs/21267.pdf Am186 and Am188 Family Instruction Set Manual]||2003-03-11||181 KB (24,861 words) - 16:02, 17 April 2022
- * L1 Cache ** L1 Instruction cache12 KB (1,895 words) - 10:17, 27 March 2020
- ** New L0 MOP cache *** 2x wider decoded instruction fetch (8 instrs/cycle, up from 4 traditional)5 KB (748 words) - 16:20, 4 July 2022
- *** One shared vector unit The Cortex-A510 has a private L1I, L1D, and cluster-wide L2 cache.15 KB (2,282 words) - 11:20, 10 January 2023