• nvidia/microarchitectures/carmel
  * Cache ...ore duplexes. The entire complex has [[cache coherency]] as well as an I/O coherent memory subsystem which is designed for communication with the various other
  2 KB (280 words) - 11:27, 30 April 2019
• amd/cores/genoa
  ...dth requirements, x16 links are repurposed for {{amd|Infinity Fabric|cache coherent inter-socket traffic}}. The raw data rate of these {{abbr|xGMI}} links is a ...ators without local memory such as a {{abbr|NIC}} using the CXL.io and CXL.cache protocols, and memory expanders using the CXL.io and CXL.memory protocols.
  14 KB (1,983 words) - 01:41, 2 April 2023
• sifive/microarchitectures/7 series
  ...well as SiFive other existing cores. Everything in the cluster is [[cache coherent]] - including any extended [[SRAM]] options as well as any custom accelerat ...t change in the 7 Series is the overhaul of the memory subsystem. The data cache and the optional tightly integrated memory (TIM) can now span two cycles, e
  4 KB (625 words) - 09:16, 28 November 2018
• cavium/ccpi
  {{cavium title|Cavium Coherent Processor Interconnect (CCPI)}}{{interconnect arch}} '''Cavium Coherent Processor Interconnect''' ('''CCPI'''') is an interconnect architecture des
  837 bytes (121 words) - 00:56, 22 June 2019
• hisilicon/hydra
  ...licon|Hi16xx}}) family of [[ARM]] server processors designed to facilitate coherent [[symmetric multiprocessing]] support. The Hydra Interface is a high-speed cache coherent [[interconnect architecture]] designed to facilitate [[symmetric multiproce
  1 KB (148 words) - 20:51, 5 May 2019
• arm holdings/microarchitectures/cortex-a34
  | L1 I-Cache / D-Cache || 8k-64k | L2 Cache || 128KB-1MB
  1 KB (179 words) - 03:34, 4 December 2021
• centaur/microarchitectures/cha
  * Cache ** L1I Cache:
  24 KB (3,792 words) - 04:37, 30 September 2022
• cea-leti/microarchitectures/tsarlet
  * L1 Cache ** L1 Instruction cache
  12 KB (1,895 words) - 10:17, 27 March 2020
• amd/packages/socket f
  ...s Opteron "{{amd|Istanbul|l=core}}" processors with six cores and 6 MiB L3 cache. It supports HyperTransport Gen 3 on I/O and inter-socket links, AMD's HT A ...DP or MP processor. On multiprocessor models all three links support cache coherent connections to other DP or MP processors.
  11 KB (1,717 words) - 17:25, 5 February 2021
• amd/packages/socket c32
  ...ort links can be used for I/O or, using an AMD proprietary protocol, cache coherent inter-socket traffic on multiprocessor systems. The 16-bit links can be ung
  7 KB (998 words) - 20:07, 7 February 2021
• amd/packages/socket g34
  ...used for I/O, e.g. connecting a GPU through a HT-PCI bridge, or for cache coherent inter-socket traffic using an AMD proprietary protocol, with flexible routi ...Pat;Kalyanasundharam, Nathan;Donley, Gregg;Lepak, Kevin;Hughes, Bill|title=Cache Hierarchy and Memory Subsystem of the AMD Opteron Processor|date=2010-04-12
  36 KB (7,214 words) - 15:50, 23 April 2022
• arm holdings/microarchitectures/neoverse v1
  ** New L0 MOP cache The Neoverse N1 has a private L1I, L1D, and L2 cache.
  5 KB (748 words) - 16:20, 4 July 2022
• alchemy/microarchitectures/au1
  ...In IDLE1 mode clocks to all core units are stopped. In IDLE0 mode the data cache continues to snoop the internal System Bus to maintain data coherency. The ...by software. It does not recognize Soft Reset, Non-Maskable Interrupt, or Cache Error exception conditions.
  13 KB (2,114 words) - 16:00, 17 April 2022
• amd/packages/socket strx4
  ...are located in the center of the die to reduce memory latency from the L3 cache.<!--Naffziger2020--> GMI2 links are serial, single-ended links with 31 tran ...e Data Fabrics of each processor on dual socket systems. S-Link is a cache coherent link to {{abbr|CCIX}} memory expanders. XGBE is a backplane Ethernet link w
  14 KB (2,188 words) - 11:45, 6 April 2024
• amd/packages/socket sp5
  On dual socket (2P) systems the cache coherent xGMI links connect the Data Fabrics of each processor. Socket SP5 processor ...d accelerators with no local memory such as a NIC using the CXL.io and CXL.cache protocols) and CXL Type 3 devices (memory expanders, using the CXL.io and C
  105 KB (21,123 words) - 02:59, 13 March 2023
• annapurna labs/graviton/graviton4
  ...ially offer additional power saving: two non-coherent virtual systems, one coherent virtual system, two metal systems, or one metal system. == Cache ==
  4 KB (586 words) - 01:50, 12 December 2023

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