• qualcomm/microarchitectures/falkor
  **** 3 instructions + 1 direct branch per cycle
  6 KB (822 words) - 13:01, 19 May 2021
• phytium/microarchitectures/xiaomi
  ...erscalar]], [[out-of-order]], 4-decode/4-dispatch pipeline with a hybrid [[branch prediction]]. ...required for retrieval of instructions from the L1. Xiaomi has a hybrid [[branch predictor]] made of a [[TAGE predictor]] and a 512-entry [[indirect predict
  7 KB (940 words) - 00:12, 8 March 2021
• amd/ryzen 7
  ...) through doubling of the L3 cache, 2x wider FPU datapath, and an improved branch prediction unit. Zen 2 also provided modest clock frequency improvements ov
  15 KB (2,095 words) - 12:18, 2 October 2022
• amd/ryzen 5
  ...) through doubling of the L3 cache, 2x wider FPU datapath, and an improved branch prediction unit. Zen 2 also provided modest clock frequency improvements ov
  14 KB (1,864 words) - 07:09, 7 October 2020
• amd/microarchitectures/zen 3
  *** Increased branch prediction bandwidth *** "zero-bubble" branch prediction
  15 KB (1,978 words) - 22:13, 6 April 2023
• loongson/godson 2
  ...speeds (doubling with each model) along with a larger cache and improved [[branch predictor]]s for triple the performance improvement each time. With the int
  6 KB (710 words) - 17:11, 11 April 2017
• loongson/godson 2/2c
  ...and almost twice the frequency as the {{\\|2B}}, along with an improved [[branch predictor]].
  4 KB (418 words) - 16:31, 13 December 2017
• intel/microarchitectures/merced
  * Branch Predictor ** Indirect branches handled with 64 entry Multiway Branch Prediction Table
  7 KB (978 words) - 21:16, 20 January 2021
• macro-operation fusion
  ...tional [[jump instruction]]. The produced output is a single operation-and-branch instruction. The final fused instruction remains as such for its remaining
  11 KB (1,614 words) - 23:01, 8 May 2020
• arm holdings/microarchitectures/cortex-a55
  * Branch predictor was re-written
  4 KB (603 words) - 04:23, 27 April 2023
• compaq/microarchitectures/alpha 21464
  * Seznec, André, et al. "Design tradeoffs for the Alpha EV8 conditional branch predictor." Computer Architecture, 2002. Proceedings. 29th Annual Internati
  2 KB (228 words) - 13:20, 31 March 2019
• arm/26-bit architectures
  ...Consequently, <code>B</code> and <code>BL</code> signed 24-bit offsets can branch to any address.
  3 KB (535 words) - 09:13, 18 February 2021
• arm/armv1
  * [[#branch_instructions|Branch Instructions]] ...=<span id="branch_instructions">'''Branch Instructions'''</span><br><small>Branch instructions order instruction processing to start elsewhere conditionally
  10 KB (1,558 words) - 15:07, 2 July 2017
• arm holdings/microarchitectures/arm6
  ...e registers, it's no longer possible to automatically save those bits on a branch and link instruction execution. Upon an exception, however, the CPSR gets c
  11 KB (1,679 words) - 18:49, 18 May 2023
• x86/avx-512
  ...r|CF|Carry Flag}} (less than), and {{abbr|PF|Parity Flag}} (unordered) for branch instructions. UCOMI instructions perform an unordered compare and only gene ...nd source2, sets the {{abbr|ZF|Zero Flag}} and {{abbr|CF|Carry Flag}} (for branch instructions) to indicate if the respective result is all zeros.
  83 KB (13,667 words) - 15:45, 16 March 2023
• ibm/microarchitectures/z14
  ** Faster branch wakeup * '''IFB''' - Instruction fetch and branch prediction
  8 KB (1,204 words) - 14:02, 23 September 2019
• intel/microarchitectures/skylake (server)
  <tr><td>Branch</td></tr>
  52 KB (7,651 words) - 00:59, 6 July 2022
• intel/microarchitectures/goldmont plus
  *** Enhanced branch prediction *** Supports faster branch redirection.
  9 KB (1,128 words) - 13:28, 17 July 2023
• pezy/pezy-scx
  ...witching done to reduce [[forwarding]] and in order mitigate the lack of [[branch prediction]]. Explicit switching of active threads is also done in order to
  6 KB (838 words) - 09:33, 9 May 2019
• mirc/identifiers/$iif
  ...condition. Because the conditional was $false, the $custom1 alias in the T branch is not called.
  3 KB (481 words) - 05:39, 4 April 2020

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