|cache=Yes should probably added at one point:

| cache = Yes * {{x86|MOVBE|<code>MOVBE</code>}} - Move Big-Endian instruction

|cache=Yes ...part identical to {{\\|Haswell}} with several enhancements, including new instruction set extensions.

|cache=Yes * Cache

| {{intel|Sandy Bridge E|l=core}} || SNB-E || Workstations & entry-level servers ...="2" | {{intel|Celeron}} || style="text-align: left;" rowspan="2" | Entry-level Budget || [[1 cores|1]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {

|side cache=128 MiB |side cache per=package

|side cache=64 MiB |side cache per=package

...=core}} || CFL-E || Mehlow || Workstation || GT2 || Workstations and entry-level servers ...(2015).png|50px|link=intel/celeron]] || {{intel|Celeron}} || 4xxx || Entry-level Budget || [[dual-core|Dual]] || {{tchk|no}} || {{tchk|no}} || {{tchk|no}} |

** 2-level predictor with 8192 entry branch history table *** Does not store target addresses. Target addresses are calculated during instruction decode

| [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk | desc 5 = '''Performance Level'''<br><table><tr><td style="width: 50px;">'''9'''</td><td>Extreme (Ryzen Th

| [[File:amd ryzen 3 logo.png|75px|link=Ryzen 3]] || {{amd|Ryzen 3}} || Entry level Performance || [[quad-core|Quad]] || {{tchk|yes}} || {{tchk|yes}} || {{tch Zen 2 inherits most of the design from {{\\|Zen+}} but improves the instruction stream bandwidth and floating-point throughput performance.

...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.

...vels of performance. Some models also support an additional [[eDRAM]] side cache. ...ontains 2 slices with 48 execution units. Has an additional [[eDRAM]] side cache.

** Instruction grouping at dispatch has been removed * Cache

|cache=Yes * Large scale cache coherency

...ementation]]. In particular, the "Alpha" refers to [[DEC]]'s [[Alpha AXP]] instruction set architecture while the "21064" refers to a "21st century"-ready {{arch| ...r CMOS-3 process ([[1 µm]]). For that reason those chips also had reduced cache amount, in addition to no FPU support.

...).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || [[6 cores|6]] - [[8 cores|8]] || {{tchk ...LFLUSHOPT</code>}} - Flush & Invalidates memory operand and its associated cache line (All L1/L2/L3 etc..)

* Cache ** Improved cache prefetch

...The PEs do not maintain [[cache-coherency]] and there is no per-PE [[data cache]]. Complex instructions are processed by the Special Function Units (SFU) l ...2 KiB of [[level 1 data cache]]. Each '''City''' is made of 64 KiB of [[L2 cache]], a number of special function units, and 4 smaller blocks called "Village

...).png|50px]] || {{intel|Xeon Bronze}} || style="text-align: left;" | Entry-level performance / <br>Cost-sensitive || 6 || {{tchk|no}} || {{tchk|no}} || {{tc ** New {{x86|CPUID}} Level Type field for "die"

** 4-way instruction decode * Cache

*** Larger [[instruction queue]] (40 entries, up from 24) *** Larger [[instruction fetch]] (48B/cycle, up from 24B/cycle)

...ssary. This core has its own 16 KiB of data cache and 4 KiB of instruction cache. ...programmed using the familiar standard GCC/GDB toolchain derived from the one developed by the RISC-V foundation. Currently two real-time operating syste

...words can be transferred each cycle between the register file and the data cache. Additionally, up to four 32-bit data words can be issued to the two FMA un ...54]] [[single-precision]] operands and is designed to sustain a single FMA instruction every 250ps (4 GHz). The multiplier itself is a [[Wallace tree]] of 4-2 car

*** Half L2 Cache Size (256 KiB, down form 512 KiB) * Cache

** Larger [[instruction queue]] (48 entries, up from 40) * Cache

** 25% more [[last level cache]] (up to 20 MiB, up from 16 MiB) * Cache

Zen 4 was first mentioned by Forrest Norrod during AMD's EPYC One Year Anniversary webinar. During the next horizon event which was held on N ...4c [referred to as “Zen 4D” in leaks] core sacrificing half of the L3 cache.)

The Neoverse N1 has a private L1I, L1D, and L2 cache. * Cache

*** Decoupled from the instruction fetch The Cortex-A76 has a private L1I, L1D, and L2 cache.

** New [[L0]] MOP cache ** 1.5x wider instruction fetch (6 instrs/cycle, up from 4)

** Additional instruction fusion cases **** New packaging scheme (improve instruction density)

...ced in [[2011]] which brought a large number of fundamental changes to the instruction set, including the introduction of 64-bit operating capabilities. ...what was previously {{\\|ARMv7}}. It covers the {{\\|A32}} and {{\\|T32}} instruction sets along with a number of new instructions. AArch32 keeps the classical A

...s full languages such as C++ and executes full programs. There is a one-to-one correspondence between the nodes in the compiler-generated graph and the CS ...are configured. The CSA can be partitioned into [[privileged]] and [[user-level]] state. This can allow a primary configuration of the fabric to run withou

...er 26 2017 with a complete lineup that ranges from a workstation featuring one vector engine (VE) card to a full supercomputer with 64 VEs. NEC disclosed *** L1I Cache:

** 1.5x larger µOP cache (2.3K entries, up from 1536) ** Data Cache

One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. ** Level 1 instruction cache switched to [[PIPT]] (from [[VIPT]])

"As one of the leading vendors of embedded ARM7TDMI applications, with extensive ex ...ction regions. These can be specified as to base address, region size, and cache/buffer properties. During debug, the ARM940T provides full debug access to

** Larger [[instruction queue]] (60 entries, up from 48) * Cache

* Cache ** L1I Cache

* Cache ** L1I Cache:

...ssets/content_type/white_papers_and_tech_docs/21086.pdf SYSCALL and SYSRET Instruction Specification Application Note]||1998-05-01|| ...https://www.amd.com/system/files/TechDocs/21267.pdf Am186 and Am188 Family Instruction Set Manual]||2003-03-11||

* L1 Cache ** L1 Instruction cache

** New L0 MOP cache *** 2x wider decoded instruction fetch (8 instrs/cycle, up from 4 traditional)

*** One shared vector unit The Cortex-A510 has a private L1I, L1D, and cluster-wide L2 cache.