EPYC 7272 - AMD

	Edit Values
	EPYC 7272
	General Info
Designer	AMD
Manufacturer	TSMC, GlobalFoundries
Model Number	7272
Part Number	100-000000079,; 100-100000079WOF
Market	Server
Introduction	August 7, 2019 (announced); August 7, 2019 (launched)
Release Price	$625.00 (tray)
Shop	Amazon
	General Specs
Family	EPYC
Series	7002
Locked	Yes
Frequency	2,900 MHz
Turbo Frequency	3,200 MHz
Clock multiplier	29
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Zen 2
Core Name	Rome
Core Family	23
Core Model	49
Core Stepping	B0
Process	7 nm, 14 nm
Technology	CMOS
MCP	Yes (3 dies)
Word Size	64 bit
Cores	12
Threads	24
Max Memory	4 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
	Electrical
TDP	120 W
	Packaging
Package	SP3, FCLGA-4094 (FC-OLGA)
Dimension	75.4 mm × 58.5 mm × 6.26 mm
Pitch	0.87 mm × 1 mm
Contacts	4094
Socket	SP3, LGA-4094

EPYC 7272 is a 64-bit dodeca-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates two compute dies fabricated on a TSMC 7 nm process and an I/O die fabricated on a GlobalFoundries 14 nm process. The 7272 has a TDP of 120 W with a base frequency of 2.9 GHz and a boost frequency of up to 3.2 GHz. This processor supports up to two-way SMP and up to 4 TiB of memory per socket.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

768 KiB

786,432 B
0.75 MiB

L1I$	384 KiB 393,216 B 0.375 MiB	12x32 KiB	8-way set associative
L1D$	384 KiB 393,216 B 0.375 MiB	12x32 KiB	8-way set associative	write-back

L2$

6 MiB

6,144 KiB
6,291,456 B
0.00586 GiB

		12x512 KiB	8-way set associative	write-back

L3$

64 MiB

65,536 KiB
67,108,864 B
0.0625 GiB

		4x16 MiB

Memory controller

This model supports up to 8 channels of up to DDR4-3200 memory^[1]^[2] with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the IFOP links between the I/O die and its only two compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK^[3]). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).^[2]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-3200
Supports ECC	Yes
Max Mem	4 TiB
Controllers	8
Channels	8
Max Bandwidth	190.7 GiB/s 195,276.8 MiB/s 204.763 GB/s 204,762.566 MB/s 0.186 TiB/s 0.205 TB/s
Bandwidth	Single 23.84 GiB/s Double 47.68 GiB/s Quad 95.37 GiB/s Hexa 143.1 GiB/s Octa 190.7 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 4.0
	Max Lanes: 128
	Configuration: x16, x8

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
SSE4a	Streaming SIMD Extensions 4a
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
SHA	SHA Extensions
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
SMT	Simultaneous Multithreading
AMD-Vi	AMD-Vi (I/O MMU virtualization)
AMD-V	AMD Virtualization
SME	Secure Memory Encryption
TSME	Transparent SME
SEV	Secure Encrypted Virtualization
SenseMI	SenseMI Technology
Boost 2	Precision Boost 2

References

↑ "AMD EPYC™ 7272". AMD.com. Retrieved October 2020.
↑ ^2.0 ^2.1 "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter", AMD Publ. #LE-70002, Rev. 02, April 2020
↑ Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). 2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:10.1109/ISSCC19947.2020.9063103

[specs-1] "AMD EPYC™ 7272". AMD.com. Retrieved October 2020.

[datasheet-2] 2.0 ^2.1 "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter", AMD Publ. #LE-70002, Rev. 02, April 2020

[isscc2020j-chiplet-3] Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). 2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:10.1109/ISSCC19947.2020.9063103

[1

[2

[3

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	EPYC 7272 - AMD#pcie +
base frequency	2,900 MHz (2.9 GHz, 2,900,000 kHz) +
clock multiplier	29 +
core count	12 +
core family	23 +
core model	49 +
core name	Rome +
core stepping	B0 +
designer	AMD +
die count	3 +
family	EPYC +
first announced	August 7, 2019 +
first launched	August 7, 2019 +
full page name	amd/epyc/7272 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has amd amd-v technology	true +
has amd amd-vi technology	true +
has amd precision boost 2	true +
has amd secure encrypted virtualization technology	true +
has amd secure memory encryption technology	true +
has amd sensemi technology	true +
has amd transparent secure memory encryption technology	true +
has ecc memory support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multiplier	true +
has simultaneous multithreading	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
is multi-chip package	true +
isa	x86-64 +
isa family	x86 +
l1$ size	768 KiB (786,432 B, 0.75 MiB) +
l1d$ description	8-way set associative +
l1d$ size	384 KiB (393,216 B, 0.375 MiB) +
l1i$ description	8-way set associative +
l1i$ size	384 KiB (393,216 B, 0.375 MiB) +
l2$ description	8-way set associative +
l2$ size	6 MiB (6,144 KiB, 6,291,456 B, 0.00586 GiB) +
l3$ size	64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldate	August 7, 2019 +
manufacturer	TSMC + and GlobalFoundries +
market segment	Server +
max cpu count	2 +
max memory	4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth	190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels	8 +
microarchitecture	Zen 2 +
model number	7272 +
name	EPYC 7272 +
package	SP3 + and FCLGA-4094 +
part number	100-000000079 + and 100-100000079WOF +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 625.00 (€ 562.50, £ 506.25, ¥ 64,581.25) +
release price (tray)	$ 625.00 (€ 562.50, £ 506.25, ¥ 64,581.25) +
series	7002 +
smp max ways	2 +
socket	SP3 + and LGA-4094 +
supported memory type	DDR4-3200 +
tdp	120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technology	CMOS +
thread count	24 +
turbo frequency	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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