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Xeon Gold 6209U
General Info
Designer	Intel
Manufacturer	Intel
Model Number	6209U
Market	Server
Introduction	April 2, 2019 (announced) April 2, 2019 (launched)
Release Price	$1,350.00 (tray)
Shop	Amazon
General Specs
Family	Xeon Gold
Series	6200
Locked	Yes
Frequency	2,100 MHz
Turbo Frequency	3,900 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	21
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Core Model	85
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	20
Threads	40
Max Memory	1 TiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	125 W
Tcase	0 °C – 87 °C
Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Xeon Gold 6209U is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6209U is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process and sports 2 AVX-512 FMA units. This microprocessor supports up 1 TiB of hexa-channel DDR4-2933 memory, operates at 2.1 GHz with a TDP of 125 W and features a turbo boost frequency of up to 3.9 GHz.

Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 1.25 MiB 1,280 KiB 1,310,720 B L1I$ 640 KiB 655,360 B 0.625 MiB 20x32 KiB 8-way set associative   L1D$ 640 KiB 655,360 B 0.625 MiB 20x32 KiB 8-way set associative write-back L2$ 20 MiB 20,480 KiB 20,971,520 B 0.0195 GiB     20x1 MiB 16-way set associative write-back L3$ 27.5 MiB 28,160 KiB 28,835,840 B 0.0269 GiB     20x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2933 Supports ECC Yes Max Mem 1 TiB Controllers 2 Channels 6 Max Bandwidth 131.13 GiB/s 134,277.12 MiB/s 140.8 GB/s 140,799.765 MB/s 0.128 TiB/s 0.141 TB/s Bandwidth Single 21.86 GiB/s Double 43.71 GiB/s Quad 87.42 GiB/s Hexa 131.13 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 48 Configuration: 1x16, x8, x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length AVX512_VNNI AVX-512 Vector Neural Network Instructions ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 EIST Enhanced SpeedStep Technology SST Speed Shift Technology TXT Trusted Execution Technology (SMX) vPro Intel vPro VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) EPT Extended Page Tables (SLAT) TSX Transactional Synchronization Extensions VMD Volume Management Device NM Node Manager KPT Key Protection Technology PTT Platform Trust Technology Run Sure Run Sure Technology (RAS Capability) MBE Ctrl Mode-Based Execute Control DL Boost Deep Learning Boost

Frequencies

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
		1	2	3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20
Normal	2,100MHz	3,900MHz	3,900MHz	3,700MHz	3,700MHz	3,600MHz	3,600MHz	3,600MHz	3,600MHz	3,400MHz	3,400MHz	3,400MHz	3,400MHz	3,000MHz	3,000MHz	3,000MHz	3,000MHz	2,800MHz	2,800MHz	2,800MHz	2,800MHz
AVX2	1,600MHz	3,800MHz	3,800MHz	3,600MHz	3,600MHz	3,400MHz	3,400MHz	3,400MHz	3,400MHz	2,900MHz	2,900MHz	2,900MHz	2,900MHz	2,600MHz	2,600MHz	2,600MHz	2,600MHz	2,400MHz	2,400MHz	2,400MHz	2,400MHz
AVX512	1,100MHz	3,700MHz	3,700MHz	3,500MHz	3,500MHz	2,800MHz	2,800MHz	2,800MHz	2,800MHz	2,400MHz	2,400MHz	2,400MHz	2,400MHz	2,100MHz	2,100MHz	2,100MHz	2,100MHz	2,000MHz	2,000MHz	2,000MHz	2,000MHz

Documents

• 2nd Generation Intel® Xeon® Scalable processors in a single-socket configuration