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Ryzen 5 3600X - AMD
Edit Values | |
Ryzen 5 3600X | |
General Info | |
Designer | AMD |
Manufacturer | TSMC |
Model Number | 3600X |
Part Number | 100-000000022, 100-100000022BOX |
Market | Desktop |
Introduction | May 27, 2019 (announced) July 7, 2019 (launched) |
Release Price | $249 |
Shop | Amazon |
General Specs | |
Family | Ryzen 5 |
Series | 3000 |
Locked | No |
Frequency | 3,800 MHz |
Turbo Frequency | 4,400 MHz |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen 2 |
Core Name | Matisse |
Process | 7 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 6 |
Threads | 12 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 95 W |
Packaging | |
Template:packages/amd/socket am4 |
Ryzen 5 3600X is a 64-bit hexa-core high-end performance x86 desktop microprocessor introduced by AMD in mid-2019. Fabricated on TSMC's 7 nm process based on the Zen 2 microarchitecture, this processor operates at 3.8 GHz with a TDP of 95 W and a Boost frequency of up to 4.4 GHz.
Cache
- Main article: Zen 2 § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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Expansions
In addition to the x4 lanes that are reserved for the chipset, the Ryen 5 3600X has x16 for a discrete graphics processor and x4 for storage (NVMe or 2 ports SATA Express).
Expansion Options |
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Graphics
This processor has no integrated graphics.
Features
[Edit/Modify Supported Features]
Supported x86 Extensions & Processor Features
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Facts about "Ryzen 5 3600X - AMD"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Ryzen 5 3600X - AMD#pcie + |
base frequency | 3,800 MHz (3.8 GHz, 3,800,000 kHz) + |
core count | 6 + |
core name | Matisse + |
designer | AMD + |
family | Ryzen 5 + |
first announced | May 27, 2019 + |
first launched | July 7, 2019 + |
full page name | amd/ryzen 5/3600x + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has amd amd-v technology | true + |
has amd amd-vi technology | true + |
has amd extended frequency range 2 | true + |
has amd precision boost 2 | true + |
has amd sensemi technology | true + |
has ecc memory support | false + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology +, Extended Frequency Range 2 + and Precision Boost 2 + |
has locked clock multiplier | false + |
has simultaneous multithreading | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l2$ description | 8-way set associative + |
l2$ size | 3 MiB (3,072 KiB, 3,145,728 B, 0.00293 GiB) + |
l3$ size | 32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) + |
ldate | 3000 + |
manufacturer | TSMC + |
market segment | Desktop + |
max cpu count | 1 + |
max memory bandwidth | 47.68 GiB/s (48,824.32 MiB/s, 51.196 GB/s, 51,196.01 MB/s, 0.0466 TiB/s, 0.0512 TB/s) + |
max memory channels | 2 + |
microarchitecture | Zen 2 + |
model number | 3600X + |
name | Ryzen 5 3600X + |
part number | 100-000000022 + and 100-100000022BOX + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |
release price | $ 249.00 (€ 224.10, £ 201.69, ¥ 25,729.17) + |
series | 3000 + |
smp max ways | 1 + |
supported memory type | DDR4-3200 + |
tdp | 95 W (95,000 mW, 0.127 hp, 0.095 kW) + |
technology | CMOS + |
thread count | 12 + |
turbo frequency | 4,400 MHz (4.4 GHz, 4,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |