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Palm Cove µarch
General Info
Arch Type	CPU
Designer	Intel
Manufacturer	Intel
Introduction	2018
Process	10 nm
Core Configs	2
Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Stages	14-19
Instructions
ISA	x86-64
Extensions	MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache	32 KiB/core 8-way set associative
L1D Cache	32 KiB/core 8-way set associative
L2 Cache	256 KiB/core 4-way set associative
L3 Cache	2 MiB/core 16-way set associative
Succession
Skylake Sunny Cove

Palm Cove is a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products.

Process Technology

Palm Cove is designed to take advantage of Intel's 10 nm process.

Architecture

Key changes from Skylake (Client)

• 10 nm process (From 14 nm)
• Front End
  • LSD is re-enabled (See Skylake § Front-end for details)
  • 50% smaller L1 instruction cache 4K page TLB (64-entry, down from 128)
• Back-end
  • Execution units
    • Port 4 now performs 512b stores (from 256b)
    • New 512b FMA unit on Port 0
    • New iDIV unit
• Memory subsystem
  • Store is now 64B/cycle (from 32B/cycle)
  • Load is now 2x64B/cycle (from 2x32B/cycle)

This list is incomplete; you can help by expanding it.

New instructions

Cannon Lake introduced a number of new instructions:

• AVX-512, specifically:
  • AVX512F - AVX-512 Foundation
  • AVX512CD - AVX-512 Conflict Detection
  • AVX512BW - AVX-512 Byte and Word
  • AVX512DQ - AVX-512 Doubleword and Quadword
  • AVX512VL - AVX-512 Vector Length
  • AVX512IFMA - AVX-512 Integer Fused Multiply-Add
  • AVX512VBMI - AVX-512 Vector Bit Manipulation
• SHA - Hardware acceleration for SHA hashing operations
• UMIP - User-Mode Instruction Prevention extension

Overview

Palm Cove is the core microarchitecture that is found in Intel's Cannon Lake SoCs. Although originally intended to be mass manufactured for all client and server markets, due to Intel's prolong 10 nm process problems, Palm Cove is getting skipped with the exception of a single chip.

See also

• Cannon Lake