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Xeon Silver 4210 - Intel
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Revision as of 19:39, 3 April 2019 by David (talk | contribs) (Memory controller)

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Xeon Silver 4210
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number4210
Part NumberCD8069503956302
S-SpecSRFBL
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$501.00 (tray)
$511.00 (box)
ShopAmazon
General Specs
FamilyXeon Silver
Series4200
LockedYes
Frequency2,200 MHz
Turbo Frequency3,200 MHz (1 core)
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingR1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores10
Threads20
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP85 W
Tcase0 °C – 78 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Silver 4210 is a 64-bit deca-core x86 mid-range performance server microprocessor introduced by Intel in early 2019. The Silver 4210 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 85 W and features a turbo boost frequency of up to 3.2 GHz.


Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$640 KiB
655,360 B
0.625 MiB
L1I$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associative 
L1D$320 KiB
327,680 B
0.313 MiB
10x32 KiB8-way set associativewrite-back

L2$10 MiB
10,240 KiB
10,485,760 B
0.00977 GiB
  10x1 MiB16-way set associativewrite-back

L3$13.75 MiB
14,080 KiB
14,417,920 B
0.0134 GiB
  10x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions

[Edit/Modify Expansions Info]

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Expansion Options
PCIe
Revision3.0
Max Lanes48
Configsx16, x8, x4


Features

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Silver 4210 - Intel#io +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipsetLewisburg +
clock multiplier22 +
core count10 +
core family6 +
core nameCascade Lake SP +
core steppingR1 +
designerIntel +
familyXeon Silver +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon silver/4210 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Extended Page Tables + and Transactional Synchronization Extensions +
has intel enhanced speedstep technologytrue +
has intel speed shift technologytrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size640 KiB (655,360 B, 0.625 MiB) +
l1d$ description8-way set associative +
l1d$ size320 KiB (327,680 B, 0.313 MiB) +
l1i$ description8-way set associative +
l1i$ size320 KiB (327,680 B, 0.313 MiB) +
l2$ description16-way set associative +
l2$ size10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) +
l3$ description11-way set associative +
l3$ size13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature351.15 K (78 °C, 172.4 °F, 632.07 °R) +
max cpu count2 +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
max pcie lanes48 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number4210 +
nameXeon Silver 4210 +
packageFCLGA-3647 +
part numberCD8069503956302 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) + and $ 511.00 (€ 459.90, £ 413.91, ¥ 52,801.63) +
release price (box)$ 511.00 (€ 459.90, £ 413.91, ¥ 52,801.63) +
release price (tray)$ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) +
s-specSRFBL +
series4200 +
smp max ways2 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2400 +
tdp85 W (85,000 mW, 0.114 hp, 0.085 kW) +
technologyCMOS +
thread count20 +
turbo frequency (1 core)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +