Edit Values | |
Snapdragon 8cx | |
General Info | |
Designer | Qualcomm, ARM Holdings |
Manufacturer | TSMC |
Market | Mobile |
Introduction | December 6, 2018 (announced) Q3, 2019 (launched) |
General Specs | |
Family | Snapdragon 800 |
Series | 800 |
Microarchitecture | |
ISA | ARMv8 (ARM) |
Microarchitecture | Cortex-A76, Cortex-A55 |
Core Name | Cortex-A76, Cortex-A55 |
Process | 7 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 8 |
Threads | 8 |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 7 W |
Packaging | |
Succession | |
Snapdragon 8cx (Snapdragon 8 Compute eXtreme) is a high-performance 64-bit ARM LTE system on a chip designed by Qualcomm and introduced in late 2018. Fabricated on TSMC's 7nm process, the 8cx features four Kryo 495 Silver high-efficiency cores operating at ? GHz along with two high-performance Kryo 495 Gold operating at ? GHz. The Snapdragon 8cx integrates the Adreno 680 GPU operation at ? MHz and features an X24 LTE modem supporting Cat 20 uplink and Cat 20 downlink. This chip supports up to ? GiB of octa-channel LPDDR4X-4266 memory.
Overview
The Snapdragon 8cx was announced by Qualcomm on December 6, 2018. The chip is what Qualcomm considers a new high tier Snapdragon aimed at always-connected PCs with higher performance and thermal headroom over traditional smartphone devices. The chip comprise of a quad-core cluster of Kryo 495 Gold (Cortex-A76) big cores and a quad-core cluster of Kryo 495 Silver (Cortex-A55) little cores.
Cache
- Main articles: Cortex-A76 § Cache and Cortex-A55
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
Integrated Memory Controller
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- all microprocessor models
- microprocessor models by qualcomm
- microprocessor models by qualcomm based on cortex-a76
- microprocessor models by qualcomm based on cortex-a55
- microprocessor models by arm holdings
- microprocessor models by arm holdings based on cortex-a76
- microprocessor models by arm holdings based on cortex-a55
- microprocessor models by tsmc
- future microprocessor models
back image | + |
core count | 8 + |
core name | Cortex-A76 + and Cortex-A55 + |
designer | Qualcomm + and ARM Holdings + |
family | Snapdragon 800 + |
first announced | December 6, 2018 + |
first launched | March 2019 + |
full page name | qualcomm/snapdragon 800/8cx + |
has ecc memory support | false + |
instance of | microprocessor + |
isa | ARMv8 + |
isa family | ARM + |
l3$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
ldate | 3000 + |
main image | + |
manufacturer | TSMC + |
market segment | Mobile + |
max cpu count | 1 + |
max memory bandwidth | 29.87 GiB/s (30,586.88 MiB/s, 32.073 GB/s, 32,072.668 MB/s, 0.0292 TiB/s, 0.0321 TB/s) + |
max memory channels | 8 + |
microarchitecture | Cortex-A76 + and Cortex-A55 + |
name | Snapdragon 8cx + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + |
series | 800 + |
smp max ways | 1 + |
supported memory type | LPDDR4X-4266 + |
tdp | 7 W (7,000 mW, 0.00939 hp, 0.007 kW) + |
technology | CMOS + |
thread count | 8 + |
word size | 64 bit (8 octets, 16 nibbles) + |