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Storm µarch
General Info
Arch Type	CPU
Designer	AppliedMicro
Manufacturer	TSMC
Introduction	2011
Process	40 nm
Core Configs	8
Pipeline
Type	Superscalar
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Instructions
ISA	ARMv8
Succession
Shadowcat

Storm is AppliedMicro first custom ARM microarchitecture for servers. Storm-based microprocessors were sold under the X-Gene 1 brand of server microprocessors.

Codenames

Codename	Description
Potenza	codename for the core and memory sub-system

Technology

Storm is fabricated on TSMC's 40 nm bluk CMOS.

Architecture

Memory Hierarchy

• Cache
  • L1I
    • 32 KiB, 8-way set associative
      • Per core
    • ECC and Parity protection
  • L1D
    • 32 KiB, 8-way set associative
      • Per core
    • 64 B/line
    • Write-through with write-combining
    • ECC and Parity protection
  • L2
    • 256 KB
      • Per process module (2 cores)
    • Inclusive of L1 write-thru data caches
    • 64 B/line
    • ECC and Parity protection
  • L3
    • 8 MiB
    • 64 B/line
    • Per chip

Bibliography

• Paramesh Gopi, Gaurav Singh, Greg Favor. "X-Gene: 64-bit ARM CPU and SoC." Hot Chips 24 Symposium (HCS), 2012 IEEE. IEEE, 2012.