Hi1612 - HiSilicon

	Edit Values
	Hi1612
	General Info
Designer	HiSilicon,; ARM Holdings
Manufacturer	TSMC
Model Number	Hi1610
Market	Server
Introduction	June 4, 2016 (announced); June 4, 2016 (launched)
	General Specs
Family	Hi16xx
Frequency	2,100 MHz
	Microarchitecture
ISA	ARMv8 (ARM)
Microarchitecture	Cortex-A57
Core Name	Cortex-A57
Process	16 nm
Technology	CMOS
Word Size	64 bit
Cores	32
Threads	32
Max Memory	256 GiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)

Hi1612 is a dotriaconta-core 64-bit ARM server microprocessor introduced by HiSilicon in mid-2016. Fabricated by TSMC on a 16 nm process, this chip incorporates 32 Cortex-A57 cores operating at 2.1 GHz. The 1612 supports up to 256 GiB of quad-channel DDR4-2133 memory.

Cache

Main article: Cortex-A57 § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

2.5 MiB

2,560 KiB
2,621,440 B

L1I$	1.5 MiB 1,536 KiB 1,572,864 B	32x48 KiB	8-way set associative
L1D$	1 MiB 1,024 KiB 1,048,576 B	32x32 KiB	8-way set associative

L2$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		32x256 KiB	8-way set associative

L3$

32 MiB

32,768 KiB
33,554,432 B
0.0313 GiB

		32x1 MiB	16-way set associative

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2133
Supports ECC	Yes
Max Mem	256 GiB
Controllers	1
Channels	4
Width	64 bit
Max Bandwidth	63.58 GiB/s 65,105.92 MiB/s 68.269 GB/s 68,268.505 MB/s 0.0621 TiB/s 0.0683 TB/s
Bandwidth	Single 15.89 GiB/s Double 31.79 GiB/s Quad 63.58 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 16
	Configuration: 2x8

Utilizing devices

HiSilicon D03

This list is incomplete; you can help by expanding it.

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Hi1612 - HiSilicon#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
core count	32 +
core name	Cortex-A57 +
designer	HiSilicon + and ARM Holdings +
family	Hi16xx +
first announced	June 4, 2016 +
first launched	June 4, 2016 +
full page name	hisilicon/kunpeng/hi1612 +
has ecc memory support	true +
instance of	microprocessor +
isa	ARMv8 +
isa family	ARM +
l1$ size	2,560 KiB (2,621,440 B, 2.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	1,024 KiB (1,048,576 B, 1 MiB) +
l1i$ description	8-way set associative +
l1i$ size	1,536 KiB (1,572,864 B, 1.5 MiB) +
l2$ description	8-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	16-way set associative +
l3$ size	32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldate	June 4, 2016 +
manufacturer	TSMC +
market segment	Server +
max cpu count	2 +
max memory	262,144 MiB (268,435,456 KiB, 274,877,906,944 B, 256 GiB, 0.25 TiB) +
max memory bandwidth	63.58 GiB/s (65,105.92 MiB/s, 68.269 GB/s, 68,268.505 MB/s, 0.0621 TiB/s, 0.0683 TB/s) +
max memory channels	4 +
microarchitecture	Cortex-A57 +
model number	Hi1610 +
name	Hi1612 +
process	16 nm (0.016 μm, 1.6e-5 mm) +
smp max ways	2 +
supported memory type	DDR4-2133 +
technology	CMOS +
thread count	32 +
used by	HiSilicon D03 +
word size	64 bit (8 octets, 16 nibbles) +

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Contents

Cache

Memory controller

Expansions

Utilizing devices