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From WikiChip
SABRE - Intel Movidius
< movidius
Edit Values | |
SABRE | |
General Info | |
Designer | Movidius |
Manufacturer | TSMC |
Model Number | SABRE |
Market | Embedded, Mobile |
General Specs | |
Frequency | 180 MHz |
Microarchitecture | |
ISA | SPARC V8 (SPARC), SHAVE (SHAVE) |
Microarchitecture | LEON3, SHAVE v2.0 |
Process | 65 nm |
Technology | CMOS |
SABRE was a test microprocessor designed by Movidius for the acceleration of machine vision. The SABRE microprocessor eventually lead to the production definition of the Myriad 1 line of vision accelerators.
Overview
SABRE is capable of 20 GLOPS at low 100s mW of power through the use of 9 execution units consisting of a SPARC V8 LEON3 core and 8 additional SHAVE v2.0 cores.
The test platform consisted of a Samsung 6410 daughtercard which incoluded an S3C6410X processor (ARM11) and a Movidius MV0108 SABRE daughtercard which had the SABRE processor.
Block diagram
References
- Tite, Teodor, et al. "moviOS: a Real-Time Multiprocessor Operating System for Multimedia Applications."
Retrieved from "https://en.wikichip.org/w/index.php?title=movidius/sabre&oldid=75081"
Facts about "SABRE - Intel Movidius"
full page name | movidius/sabre + |
instance of | microprocessor + |
ldate | 1900 + |