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Xeon D-2161I - Intel
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Xeon D-2161I
skylake-de (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberD-2161I
Part NumberFH8067303534104
S-SpecSR3ZN
MarketServer, Embedded
Release Price$962.00
ShopAmazon
General Specs
FamilyXeon D
SeriesD-2000
LockedYes
Frequency2,200 MHz
Turbo Frequency3,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureSkylake (server)
Core NameSkylake-DE
Core SteppingM1
Process14 nm
TechnologyCMOS
MCPYes (2 dies)
Word Size64 bit
Cores12
Threads24
Max Memory512 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP90 W

Xeon D-2161I is a 64-bit dodeca-core high-performance x86 microserver processor set to be introduced by Intel in early 2018. Fabricated on Intel's 14nm+ process based on the Skylake microarchitecture, this chip operates at 2.2 GHz with a TDP of 90 W.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

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Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem512 GiB
Controllers2
Channels4
Max Bandwidth79.47 GiB/s
81,377.28 MiB/s
85.33 GB/s
85,330.263 MB/s
0.0776 TiB/s
0.0853 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s

Expansions

[Edit/Modify Expansions Info]

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Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: x16, x8, x4


Features

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (2 Units)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
VMDVolume Management Device
IPTIdentity Protection Technology
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_d/d-2161i&oldid=73777"
Facts about "Xeon D-2161I - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon D-2161I - Intel#package + and Xeon D-2161I - Intel#pcie +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier22 +
core count12 +
core nameSkylake DE +
core steppingM1 +
designerIntel +
die count2 +
familyXeon D +
first announcedFebruary 7, 2018 +
first launchedFebruary 7, 2018 +
full page nameintel/xeon d/d-2161i +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size384 KiB (393,216 B, 0.375 MiB) +
l1i$ description8-way set associative +
l1i$ size384 KiB (393,216 B, 0.375 MiB) +
l2$ description16-way set associative +
l2$ size12 MiB (12,288 KiB, 12,582,912 B, 0.0117 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateFebruary 7, 2018 +
main imageFile:skylake-de (front).png +
manufacturerIntel +
market segmentServer + and Embedded +
max cpu count1 +
max hsio lanes20 +
max memory524,288 MiB (536,870,912 KiB, 549,755,813,888 B, 512 GiB, 0.5 TiB) +
max memory bandwidth79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels4 +
microarchitectureSkylake (server) +
model numberD-2161I +
nameXeon D-2161I +
number of avx-512 execution units1 +
packageFCBGA-2518 +
part numberFH8067303534104 +
part ofEdge Server and Cloud SKUs +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 962.00 (€ 865.80, £ 779.22, ¥ 99,403.46) +
s-specSR3ZN +
seriesD-2000 +
smp max ways1 +
supported memory typeDDR4-2133 +
tdp90 W (90,000 mW, 0.121 hp, 0.09 kW) +
technologyCMOS +
thread count24 +
turbo frequency (1 core)3,000 MHz (3 GHz, 3,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +