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Exynos 8895 - Samsung
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Revision as of 20:50, 7 December 2023 by 187.95.9.187 (talk) (added complete information about 8895)

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Exynos 8895
General Info
DesignerSamsung,
ARM Holdings
ManufacturerSamsung
Model Number8895
MarketMobile
IntroductionFebruary 23, 2017 (announced)
March 29, 2017 (launched)
General Specs
FamilyExynos
SeriesExynos 9
LockedNo
Frequency2314 MHz, 1690 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureM2, Cortex-A53
Core NameExynos M2, Cortex-A53
Process10 nm
TechnologyCMOS
MCPYes
Word Size64 bit
Cores8
Threads8
Max Memory8 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Vcore0.905 V-1.22 V
TDP5 W
cTDP down12 W
cTDP down frequency2314 MHz
cTDP up16 W
cTDP up frequency2810 MHz
OP Temperature-15 °C – 115 °C
Tjunction115 – 115
Succession
Contemporary
Exynos 9820

Exynos 8895 is a 64-bit octa-core ARM high performance mobile system on a chip designed by Samsung and introduced in mid-2019. The processor is fabricated on Samsung's 10nm EUV (Extreme Ultra Violet) FinFET process and features 8 cores in a tri-cluster configuration consisting of 4 Mongoose 2 big cores running at 2314 to 2810 MHz, 4 Cortex-A53 little cores at 1690 to 2002 MHz. This chip supports up to 8 GiB of dual-channel 16-bit LPDDR4X-1794 memory and incorporates a Mali-G71 MP20 GPU. The 8895 incorporates an LTE modem supporting cat 16 download and upload.

Cache

Main articles: Mongoose 2 § Cache and Cortex-A53 § Cache

For the Mongoose 2 core cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$192 KiB
196,608 B
0.188 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  2x512 KiB16-way set associative 
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB  

For the Cortex-A53 cluster:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$256 KiB
262,144 B
0.25 MiB
L1I$128 KiB
131,072 B
0.125 MiB
2x64 KiB4-way set associative 
L1D$128 KiB
131,072 B
0.125 MiB
2x64 KiB16-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associative 

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3588
Supports ECCNo
Max Mem8 GiB
Frequency1800 MHz
Controllers2
Channels2
Width32 bit
Max Bandwidth28.64 GiB/s
29,327.36 MiB/s
30.752 GB/s
30,751.966 MB/s
0.028 TiB/s
0.0308 TB/s
Bandwidth
Single 14.32 GiB/s
Double 28.64 GiB/s

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUMali-G71
DesignerARM Holdings
Execution Units20Max Displays2
Frequency546 MHz
0.546 GHz
546,000 KHz
Burst Frequency850 MHz
0.85 GHz
850,000 KHz
OutputDSI
Standards
DirectX12
OpenCL2
OpenGL ES3.2
OpenVG1.1
Vulkan1.0


Codec Encode Decode150
HEVC (H.265) ✔ ✔
MPEG-4 AVC (H.264) ✔ ✔
VP9 ✔ ✔

All at 4K UHD 60fps.

Wireless

Antu network-wireless-connected-100.svgWireless Communications
Cellular
4G
LTE Advanced
UE Cat DL16 (1000 Mbps)
UE Cat UL16 (280 Mbps)

ISP

  • 28MP Rear
  • 16MP Front
  • 28MP+28MP Dual

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported ARM Extensions & Processor Features
NEONAdvanced SIMD extension
CRC32CRC-32 checksum Extension
CryptoCryptographic Extension
FPFloating-point Extension

Utilizing devices

  • Samsung Galaxy Note 8
  • Samsung Galaxy S8
  • Samsung Galaxy S8+
Retrieved from "https://en.wikichip.org/w/index.php?title=samsung/exynos/8895&oldid=101982"
Facts about "Exynos 8895 - Samsung"
RDF feed
base frequency2,314 MHz (2.314 GHz, 2,314,000 kHz) + and 1,690 MHz (1.69 GHz, 1,690,000 kHz) +
core count8 +
core nameExynos M2 + and Cortex-A53 +
core voltage (max)1.22 V (12.2 dV, 122 cV, 1,220 mV) +
core voltage (min)0.905 V (9.05 dV, 90.5 cV, 905 mV) +
designerSamsung + and ARM Holdings +
familyExynos +
first announcedFebruary 23, 2017 +
first launchedMarch 29, 2017 +
full page namesamsung/exynos/8895 +
has 4g supporttrue +
has ecc memory supportfalse +
has locked clock multiplierfalse +
has lte advanced supporttrue +
instance ofmicroprocessor +
integrated gpuMali-G71 +
integrated gpu base frequency546 MHz (0.546 GHz, 546,000 KHz) +
integrated gpu designerARM Holdings +
integrated gpu execution units20 +
integrated gpu max frequency850 MHz (0.85 GHz, 850,000 KHz) +
is multi-chip packagetrue +
isaARMv8 +
isa familyARM +
l1$ size192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1d$ description8-way set associative + and 16-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) + and 128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative + and 8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
ldateMarch 29, 2017 +
manufacturerSamsung +
market segmentMobile +
max cpu count1 +
max junction temperature115 K (-158.15 °C, -252.67 °F, 207 °R) +
max memory8,192 MiB (8,388,608 KiB, 8,589,934,592 B, 8 GiB, 0.00781 TiB) +
max memory bandwidth28.64 GiB/s (29,327.36 MiB/s, 30.752 GB/s, 30,751.966 MB/s, 0.028 TiB/s, 0.0308 TB/s) +
max memory channels2 +
max operating temperature115 °C +
microarchitectureM2 + and Cortex-A53 +
min junction temperature115 K (-158.15 °C, -252.67 °F, 207 °R) +
min operating temperature-15 °C +
model number8895 +
nameExynos 8895 +
process10 nm (0.01 μm, 1.0e-5 mm) +
seriesExynos 9 +
smp max ways1 +
supported memory typeLPDDR4X-3588 +
tdp5 W (5,000 mW, 0.00671 hp, 0.005 kW) +
tdp down12 W (12,000 mW, 0.0161 hp, 0.012 kW) +
tdp down frequency2,314 MHz (2.314 GHz, 2,314,000 kHz) +
tdp up16 W (16,000 mW, 0.0215 hp, 0.016 kW) +
tdp up frequency2,810 MHz (2.81 GHz, 2,810,000 kHz) +
technologyCMOS +
thread count8 +
used bySamsung Galaxy Note 8 +, Samsung Galaxy S8 + and Samsung Galaxy S8+ +
user equipment category downlink16 +
user equipment category uplink16 +
word size64 bit (8 octets, 16 nibbles) +