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SP4r2
General Info
Designer	AMD
Introduction	February 21, 2018 (launched)
Market	Embedded
Microarchitecture	Zen
TDP	55 W 55,000 mW 0.0738 hp 0.055 kW
Package
Name	SP4r2
Type	FC-OBGA
Dimension	45 mm 4.5 cm 1.772 in × 45 mm 4.5 cm 1.772 in
Pitch	0.8 mm 0.0315 in
Contemporary
SP4

SP4r2 and its contemporary SP4 are microprocessor packages of AMD EPYC 3000 "Snowy Owl" embedded processors. Server processors of the same generation (EPYC 7001) use Socket SP3.

Overview

SP4 and SP4r2 are ball grid array packages with 0.8 mm non-uniform pitch, 45 mm × 45 mm in size, with flip chip die attachment and a stiffener frame. The processors using these packages are members of AMD's x86 CPU Family 17h with CPU cores based on the Zen microarchitecture, and are fabricated on a GlobalFoundries 14 nm process.

SP4r2 carries a "Zeppelin" ZP-B2 die. AMD used this die in various revisions for EPYC 7001 server and embedded processors, first generation Ryzen Threadripper HEDT and Ryzen desktop processors; see CPU Family 17h. The pin compatible SP4 package uses two of these dies. It integrates eight CPU cores, two memory controllers, two 16-lane multi-function I/O interfaces and other I/O facilities. Both package types are intended for single processor systems so xGMI links are not supported. The multi-function I/O interfaces can be configured as PCIe, SATA, SATA Express, or XGBE links. The latter support the 10GBASE-KR, 1000BASE-KX, and SGMII (10/100/1000 Mbit/s) backplane Ethernet protocols.

Features

• Lidless ball grid array package with stiffener frame, 45 mm × 45 mm
  •  ? contacts, 0.8 mm non-uniform pitch
  • Organic substrate, flip chip die attachment

• 2 × 72 bit DDR4 SDRAM interface
  • Up to 1333 MHz, PC4-21333 (DDR4-2666), 42.67 GB/s total raw bandwidth
  • Up to 2 DIMMs/channel
  • UDIMM, RDIMM, LRDIMM, NVDIMM-N types
  • ECC support
  • Memory addressing up to ? GiB/channel
  • Max. total memory capacity 512 GiB using 4 × 128 GiB LRDIMMs

• Two multi-function I/O interfaces P0, G0

Lane	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PCIe	x16
	x8								x8
	x4				x4				x4				x4
	x2		x2		x2		x2		x2		x2		x2		x2
	x1	x1	x1	x1	x1	x1	x1	x1	x1	x1	x1	x1	x1	x1	x1	x1
SATAe													1		0
SATA									7	6	5	4	3	2	1	0
XGBE									3	2	1	0
	PHY 4				PHY 3				PHY 2				PHY 1		PHY 0

• PCIe Gen 1, 2, 3 (8 GT/s) protocol supported on all interfaces
  • 16 lanes, up to 8 ports per interface configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x4 + 4x1 + 1x8)
  • Max. 7 PCIe ports in each 8-lane subset (e.g. 0x8 + 8x1 is not possible)
  • Max. 7 PCIe ports per interface if any lane is configured as SATA port
  • Different PCIe generations supported on the ports in the same interface
  • Lane polarity inversion, per port lane reversal
  • Up to 32 PCIe lanes total

• SATA Express supported on the lowest four lanes of P0
  • Combines PCIe and SATA controllers on the same two lanes with a GPIO pin for a device to indicate its controller type
  • Up to 2 ports total

• SATA Gen 1, 2, 3 (6 Gb/s) protocol supported on the lower 8 lanes of P0

• XGBE protocols supported on lanes 4-7 of P0

• Five PHY groups on each interface
  • Lanes sharing a PHY group must use the same protocol (PCIe, SATA, XGBE)

• 4 × USB 1.1, 2.0, 3.1 Gen 1 (5 Gb/s) ports

• Low speed interfaces: eMMC, UART, LPC, SPI/eSPI, I²C, SMBus, GPIO

Processors using package SP4r2

Model	Cores	Threads	L2$	L3$	Base Frequ.	Turbo one core	Memory (1DPC)	Memory channels	Tjmin	Tjmax	cTDP↓	TDP	Launched	Price	LTB	OPN
3101	4	4	2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB	8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB	2.1 GHz 2,100 MHz 2,100,000 kHz	2.9 GHz 2,900 MHz 2,900,000 kHz	DDR4-2666	2	0 °C 273.15 K 32 °F 491.67 °R	95 °C 368.15 K 203 °F 662.67 °R		35 W 35,000 mW 0.0469 hp 0.035 kW	21 February 2018		2028	PE3101BIR4KAF
3151	4	8	2 MiB 2,048 KiB 2,097,152 B 0.00195 GiB	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	2.7 GHz 2,700 MHz 2,700,000 kHz	2.9 GHz 2,900 MHz 2,900,000 kHz	DDR4-2666	2	0 °C 273.15 K 32 °F 491.67 °R	95 °C 368.15 K 203 °F 662.67 °R		45 W 45,000 mW 0.0603 hp 0.045 kW	21 February 2018		2028	PE3151BJR48AF
3201	8	8	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	1.5 GHz 1,500 MHz 1,500,000 kHz	3.1 GHz 3,100 MHz 3,100,000 kHz	DDR4-2133	2	0 °C 273.15 K 32 °F 491.67 °R	95 °C 368.15 K 203 °F 662.67 °R		30 W 30,000 mW 0.0402 hp 0.03 kW	21 February 2018		2028	PE3201BHR88AF
3251	8	16	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	2.5 GHz 2,500 MHz 2,500,000 kHz	3.1 GHz 3,100 MHz 3,100,000 kHz	DDR4-2666	2	0 °C 273.15 K 32 °F 491.67 °R	105 °C 378.15 K 221 °F 680.67 °R		55 W 55,000 mW 0.0738 hp 0.055 kW	21 February 2018	$ 315.00 € 283.50 £ 255.15 ¥ 32,548.95	2028	PE3251BGR88AF
3255	8	16	4 MiB 4,096 KiB 4,194,304 B 0.00391 GiB	16 MiB 16,384 KiB 16,777,216 B 0.0156 GiB	2.5 GHz 2,500 MHz 2,500,000 kHz	3.1 GHz 3,100 MHz 3,100,000 kHz	DDR4-2666	2	-40 °C 233.15 K -40 °F 419.67 °R	105 °C 378.15 K 221 °F 680.67 °R	30 W 30,000 mW 0.0402 hp 0.03 kW	55 W 55,000 mW 0.0738 hp 0.055 kW			2028	PE3255BGR88AF
Count: 5

Photos

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Package Diagrams

SP4 package

SP4r2 package

Pin Map

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Bibliography

• "Product Brief: AMD EPYC™ Embedded 3000 Family", AMD Publ. #1887102, 2018
• "Product Brief: AMD EPYC™ Embedded 3000 Family", AMD Publ. #1887102, Rev. E, 2019
• "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors", AMD Publ. #54945, Rev. 1.14, April 15, 2017
• "Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors", AMD Publ. #54945, Rev. 3.00, April 14, 2019
• "Revision Guide for AMD Family 17h Models 00h-0Fh Processors", AMD Publ. #55449, Rev. 1.19, December 2019
• "Embedded Processor Specifications". AMD.com.

See also

• Package SP4
• Socket SP3
• Socket TR4