• intel/cores/coffee lake er
  |predecessor link=intel/cores/coffee_lake_e ...C246). The microprocessor is connected to the chipset via 4 of the chip's 20 PCIe lanes using Intel's proprietary {{intel|Direct Media Interface}} 3.0 (
  5 KB (721 words) - 12:41, 12 June 2023
• amd/packages/fp6
  ...32-bit channels of [[LPDDR4x]] memory, two PCIe Gen 3 I/O interfaces with 20 lanes total, four digital display interfaces, four USB 3.2 Gen 2 ports, fou All FP6 packages carry a monolithic die which integrates eight CPU cores, two memory controllers, a graphics processor, and a controller hub. "Renoi
  20 KB (3,273 words) - 17:47, 10 May 2023
• amd/packages/socket g34
  ...chitecture, and Family 15h featuring up to 8 compute units (not exactly 16 cores) based on the {{amd|Bulldozer|l=arch}} and {{amd|Piledriver|l=arch}} microa ** AMD Turbo CORE technology with per core power gating (Fam. 15h)
  36 KB (7,214 words) - 15:50, 23 April 2022
• amd/epyc/7713p
  |frequency=2,000 MHz |turbo frequency=3,675 MHz
  4 KB (682 words) - 13:35, 18 May 2021
• amd/epyc/7663
  |frequency=2,000 MHz |turbo frequency=3,500 MHz
  4 KB (683 words) - 12:06, 25 May 2021
• amd/epyc/7713
  |frequency=2,000 MHz |turbo frequency=3,675 MHz
  4 KB (683 words) - 12:04, 25 May 2021
• intel/core i7/i7-12700k
  |frequency=3,600 MHz |turbo frequency=4,900 MHz
  6 KB (865 words) - 23:57, 19 March 2023
• intel/core i7/i7-12700kf
  |frequency=3,600 MHz |turbo frequency=4,900 MHz
  4 KB (742 words) - 15:41, 3 November 2021
• intel/core i5/i5-12600k
  |frequency=3,700 MHz |turbo frequency=4,900 MHz
  6 KB (850 words) - 03:53, 21 July 2022
• intel/core i5/i5-12600kf
  |frequency=3,700 MHz |turbo frequency=4,900 MHz
  4 KB (727 words) - 15:41, 3 November 2021
• amd/embedded/t40n
  |frequency=1,000 MHz |turbo frequency=1,100 MHz
  7 KB (1,121 words) - 05:33, 24 March 2023
• amd/embedded/t56e
  |frequency=1,650 MHz |turbo frequency=1,815 MHz
  7 KB (1,094 words) - 05:33, 24 March 2023
• amd/embedded/t56n
  |frequency=1,650 MHz |turbo frequency=1,815 MHz
  7 KB (1,122 words) - 05:33, 24 March 2023
• amd/packages/socket sp5
  ...grating one I/O die and up to 12 Core Complex Dies which contain eight CPU cores each. A {{abbr|GMI}}3 link connects each CCD to the IOD. ...PSP}}, SMUs and other IPs, primarily for temperature monitoring, power and frequency control. Physically they use the PCIe Gen 3 protocol.
  105 KB (21,123 words) - 02:59, 13 March 2023
• amd/packages/socket am5
  ...AMD]] for their fifth generation {{amd|Ryzen}} desktop processors with CPU cores based on the {{amd|Zen 4|l=arch}} microarchitecture, the successor to {{\\| This compares to two [[DDR4]] channels, 20 + 4 lanes PCIe Gen 3/4, four
  19 KB (3,162 words) - 17:35, 11 May 2023
• intel/microarchitectures/raptor lake
  |cores=24 |cores 2=16
  9 KB (1,220 words) - 00:23, 17 January 2023
• intel/core i9/i9-13900k
  |first launched=October 20,2022 |frequency=2,200 MHz
  6 KB (929 words) - 01:17, 3 October 2022
• intel/core i9/i9-13900kf
  |first launched=October 20,2022 |frequency=2,200 MHz
  5 KB (802 words) - 21:48, 16 December 2022
• intel/core i7/i7-13700k
  |first launched=October 20,2022 |frequency=2,500 MHz
  6 KB (869 words) - 19:34, 20 March 2024
• intel/core i7/i7-13700kf
  |first launched=October 20,2022 |frequency=2,500 MHz
  5 KB (745 words) - 14:49, 20 February 2023

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