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  • |s-spec=SR2JL |bus rate=4 GT/s
    4 KB (649 words) - 16:22, 13 December 2017
  • |s-spec=SR2F1 |bus rate=4 GT/s
    4 KB (654 words) - 17:22, 26 March 2018
  • Introduced in late 2002, Intel's 90 nm process became the first volume production to introduce [[strained si
    3 KB (354 words) - 03:09, 17 August 2023
  • ...el's 10nm (e.g., Samsung's metal pitch just 1 nanometer shorter than Intel's 14nm). {{see also|intel/process|l1=Intel's Process Technology History}}
    14 KB (1,903 words) - 06:52, 17 February 2023
  • ...een 90-102 million [[transistors per square millimeter]] based on WikiChip's own analysis. ...f the Intel 7 process''' in late 2022 with the introduction of the company's 13th Generation Core processors based on the {{intel|Raptor Lake|l=arch}} m
    13 KB (1,941 words) - 02:40, 5 November 2022
  • ...en 130-230 million [[transistors per square millimeter]] based on WikiChip's own analysis. ...p in 2023. On February 8 2017, Intel announced a $7B investment in Arizona's Fab 42 which will eventually produce chips on a 7 nm process. On March 23 2
    11 KB (1,662 words) - 02:58, 2 October 2022
  • ...sulted in a smaller, 9.26 µm², 6T SRAM. The process used 200 mm [[wafer]]s, [[Wikipedia:SiO2|SiO<sub>2</sub>]] dielectric and [[wikipedia:polysilicon| * Brand, Adam, et al. "Intel’s 0.25 micron, 2.0 volts logic process technology." Intel Technology Journal
    6 KB (661 words) - 16:18, 21 August 2022
  • ...plant was later sold to [[Intel]] where it continued to manufacture Intel's line of {{intel|XScale|l=arch}} processors.
    5 KB (586 words) - 22:44, 4 April 2022
  • {{see also|dec/process|l1=DEC's Process Technology History}} DEC's half-micron process, '''CMOS-5''', which was used for their microprocessors
    4 KB (438 words) - 06:15, 20 July 2018
  • * Meguro, S., et al. "Hi-CMOS III technology." Electron Devices Meeting, 1984 Internati
    1 KB (138 words) - 12:57, 23 October 2022
  • ...hrink of their previous generation [[7 µm]] nMOS also developed by [[HP]]'s Loveland Division. The shrink was done in the hope they could double the sp
    2 KB (325 words) - 06:22, 20 July 2018
  • ...e Intel documents refer to it as "0.35µm"). The process was used in Intel's {{intel|P55C}} ({{x86|MMX}}) and {{intel|P6|l=arch}} {{intel|Klamath|l=core
    2 KB (225 words) - 06:11, 20 July 2018
  • ...public on February 25, 2000. At the time, becoming the largest IPO for a U.S. semiconductor company in history.
    2 KB (189 words) - 17:29, 3 December 2016
  • ...erformance by opportunistically and automatically increasing the processor's [[clock generator|clock]] frequency. This feature automatically kicks in on ...e cores, the lower the highest clock frequency Turbo Boost can allow as it's easier to exceed various electrical limits. For example, a [[dual-core]] 2
    7 KB (990 words) - 14:39, 23 July 2022
  • ...nductor]] company. MediaTek designs [[microprocessor]]s, [[system on chip]]s and various other chips for mobile devices, home entertainment, [[wearables * 2007: [[Analog Devices]]'s baseband chips product lines
    2 KB (174 words) - 14:22, 29 December 2020
  • ...in the world. In [[1975]] MIL ceased to operate (note that various of MIL's products continued to be manufactured in the United States by [[MiniMicroMa * {{mil|MF7???}}, second source of [[Intel]]'s {{intel|1103}} 1K DRAM
    2 KB (289 words) - 07:23, 29 April 2016
  • | s-spec = SL2KH | s-spec 2 = SL2RQ
    3 KB (316 words) - 16:25, 13 December 2017
  • | s-spec = SL2KJ | s-spec 2 = SL2RR
    3 KB (319 words) - 16:25, 13 December 2017
  • | s-spec = SL2RS | s-spec 2 = SL2Y7
    3 KB (313 words) - 16:25, 13 December 2017
  • | s-spec = SL3HH | s-spec 2 = SL32Q
    3 KB (366 words) - 16:25, 13 December 2017

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