• zhaoxin/microarchitectures/wudaokou
  |cores 3=8 |extension 8=AVX
  9 KB (1,134 words) - 13:02, 17 June 2019
• zhaoxin/kaixian
  ...booting all modern operating systems such as Red Hat Enterprise Linux and Windows 10. ...er of enhancements including extending the architecture to support up to [[8 cores]]. With many respect they are very similar to VIA's {{via|QuadCore}}.
  6 KB (741 words) - 08:23, 27 May 2019
• intel/microarchitectures/comet lake
  |extension 8=SSE4.2 |l1i desc=8-way set associative
  10 KB (1,357 words) - 18:48, 13 September 2022
• amd/packages/socket tr4
  ...I/O interfaces, eight USB 3.1 Gen 1 ports, and up to 16 SATA Gen 3 ports. 8-layer motherboards are required to route these signals. ...ced under the lid around the chiplet periphery on the top side, and in two windows in the pad grid on the bottom side. TR4 packages use solder as {{abbr|TIM}}
  86 KB (17,313 words) - 02:48, 13 March 2023
• amd/packages/socket sp3
  ...s]] under the lid around the chiplet periphery on the top side, and in two windows in the pad grid on the bottom side. Type-1/2 packages integrate one central I/O die and 2, 4, 6, or 8 identical Core Complex Dies which contain eight CPU cores each, populated i
  110 KB (21,122 words) - 02:46, 13 March 2023
• arm holdings/microarchitectures/cortex-a76
  |cores 5=8 |l2 desc=8-way set associative
  14 KB (2,183 words) - 17:15, 17 October 2020
• intel/microarchitectures/sunny cove
  |cores 3=8 |cores 8=20
  34 KB (5,187 words) - 06:27, 17 February 2023
• amd/List of AMD publications
  ...Guide - Model 8 (June, 1999).pdf|AMD-K6-2 Processor Revision Guide - Model 8]]||1999-06|| |21892||||[https://www.amd.com/system/files/TechDocs/21892.pdf ÉlanSC400 and Windows CE uforCE Demonstration System User's Manual]||2003-03-27||
  181 KB (24,894 words) - 16:24, 12 June 2024
• mirc/identifiers/$min
  <source lang="mIRC">//echo -a $min(11 2 3 5 8 13) $min(11,2,3,5,8,13)</source> ...1:black 02:blue 14:grey 3:green 13:magenta 5:maroon 6:purple 04:red 7:tan 8:yellow 0:white)</source>
  2 KB (316 words) - 18:09, 22 January 2022
• alchemy/au1200-333mgc
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  6 KB (862 words) - 01:16, 19 March 2022
• alchemy/au1200-333mgd
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  6 KB (865 words) - 01:18, 19 March 2022
• alchemy/au1200-333mgf
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  6 KB (872 words) - 01:19, 19 March 2022
• alchemy/au1200-333mgi
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  6 KB (873 words) - 01:23, 19 March 2022
• alchemy/au1200-400mgc
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  6 KB (859 words) - 01:24, 19 March 2022
• alchemy/au1200-400mgd
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  6 KB (858 words) - 01:26, 19 March 2022
• alchemy/au1200-500mgc
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  6 KB (853 words) - 01:27, 19 March 2022
• alchemy/au1200-500mgd
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  6 KB (852 words) - 01:30, 19 March 2022
• alchemy/au1210-333mgd
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  5 KB (645 words) - 01:47, 19 March 2022
• alchemy/au1210-333mgf
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  5 KB (652 words) - 01:50, 19 March 2022
• alchemy/au1210-400mgd
  ...memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, * TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color
  5 KB (645 words) - 01:51, 19 March 2022

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