x86
Instruction Set Architecture

General

• History
• Families

Variants

• x86-16
• x86-32
• x86-64

Topics

• Instructions
• Addressing Modes
• Registers
• Model-Specific Register
• Assembly
• Interrupts
• Micro-Ops
• Timer
• Calling Convention
• Microarchitectures
• CPUID

CPUIDs

• AMD's CPUIDs
• Intel's CPUIDs

Modes

• Real
• Protected
• Long

Extensions(all)

• 3DNow!
• ABM
• ADX
• AES
• AMX
• AVX
• AVX2
• AVX-512
• BMI1
• BMI2
• CLMUL
• E3DNow!
• EMMX
• F16C
• FMA3
• FMA4
• FPU
• MKTME
• MMX
• MPX
• PMEM
• PREFETCH
• RdRAND
• SEV
• SGX
• SHA
• SME
• SMM
• SMX
• SSE
• SSE2
• SSE3
• SSE4.1
• SSE4.2
• SSE4a
• SSE5
• SSSE3
• TBM
• TME
• TSME
• TSX
• XOP

Below is a list of AMD's CPUID broken down by their respective core names and microarchitecture:

This article is a work in progress!

CPUIDs

Family 23

Microarchitecture	Core	Extended Family	Family	Extended Model	Model
Zen 4	Genoa
Zen 3	Milan
Zen 2	Matisse	0x8	0xF	0x7	0x1	Family 23 Model 113
	Rome, Castle Peak	0x8	0xF	0x3	0x1	Family 23 Model 49
Zen+	Picasso	0x8	0xF	0x1	0x8	Family 23 Model 24
	Pinnacle Ridge	0x8	0xF	0x0	0x8	Family 23 Model 8
Zen	Dali	0x8	0xF	0x1	0x8	Family 23 Model 24
	Raven Ridge	0x8	0xF	0x1	0x1	Family 23 Model 17
	Naples, Whitehaven, Summit Ridge, Snowy Owl	0x8	0xF	0x0	0x1	Family 23 Model 1